Question

Using Verilog, write a simulation code that shows the function g(w, x, y, z) = wxyz + w’x’y’z+w’x’yz’+w’xy’z’+wx’y’z’ using a 4 to 16 decoder that is built with two 3 to 8 decoders.

The 3 to 8 source code I'm using is:

module Dec3to8(
   input[2:0] A,
   input E,
   output[7:0] D
   );
   assign D[0] = E & ~A[2] & ~A[1] & ~A[0];
   assign D[1] = E & ~A[2] & ~A[1] & A[0];
   assign D[2] = E & ~A[2] & A[1] & ~A[0];
   assign D[3] = E & ~A[2] & A[1] & A[0];
   assign D[4] = E & A[2] & ~A[1] & ~A[0];
   assign D[5] = E & A[2] & ~A[1] & A[0];
   assign D[6] = E & A[2] & A[1] & ~A[0];
   assign D[7] = E & A[2] & A[1] & A[0];
endmodule

The source code for the 4 to 16 decoder using the two 3 to 8 decoders is:

module Dec4to16(
   input[3:0] A,
   output[15:0] D
   );
   Dec3to8 dec1(.A(A[2:0]), .E(A[3]), .D(D[15:8]));
   Dec3to8 dec2(.A(A[2:0]), .E(~A[3]), .D(D[7:0]));
endmodule

and the simulation code I'm using is:

module Dec4to16_Sim( );

reg[3:0] A_t;
wire[15:0] D_t;

Dec4to16 UUT(
.A(A_t),   
.D(D_t)
);
initial begin
A_t = 4'b000;
end
always #10 A_t = A_t + 1;

endmodule

These codes don't show the minterms for the function posted above and I'm not sure how to that.

Answer 1

For the required output you have to take one more output of 1 bit.

module Dec4to16(
input[3:0] A,

output g,
output[15:0] D
);
   Dec3to8 dec1(.A(A[2:0]), .E(A[3]), .D(D[15:8]));
   Dec3to8 dec2(.A(A[2:0]), .E(~A[3]), .D(D[7:0]));

assign g = D[1] or D[2] or D[4] or D[8] or D[15];
endmodule

Simulation code :-

module Dec4to16_Sim( );

reg[3:0] A_t;

wire g_t;
wire[15:0] D_t;

Dec4to16 UUT(
.A(A_t),

.g(g_t),
.D(D_t)
);
initial begin
A_t = 4'b000;
end
always #10 A_t = A_t + 1;

endmodule

Note that i have taken the decoders whose outputs are active high.