Question

Please code the following in Verilog:

Write the HDL gate-level hierarchical description of a four-bit adder-subtractor for unsigned binary numbers similar to the following circuit. You can instantiate the four-bit full adder described in the following example code Figure 4.13a, 4-Bit adder-subtractor without overflow Inputs: 4-Bit A, 4-Bit B, and Mode M (0-add/1-subtract) Interfaces: Carry Bits C1, C2, C3 Outputs: Carry C (1 Bit, C4), Sum S (4 bit) Bo A FA FA FA FA module Add half (input a, b, output c out, sum), optional endmodule module Add full (input a, b, c in, output c out, sum) xor G1 (sum, a, b); // Gate instance names are Decrease Font Size and G2 (c out, a, b); // See Fig. 4.8 // wl is c out; w2 is sum wire w1, w2, w3; Add half M1 (a, b, wl, w2); Add half M0 (w2, c in, w3, sum) or (c out, wl, w3) endmodule module Add rca4 (input [3:0] a, b, input c in output c_out, output [3:0] sum); // Intermediate carries Add full MO (a [0], b[0], c in, c inl, sum [O]) Add full M1 (a[l, b[1], c inl, c in2, sum [1]) Add full M2 (a[2], b[2], c_in2, c in3, sum [2]); Add full M3 (a [3], b[3], c in3, c out, sum [3]) endmodule module sum, ) Add-rca-8 (input [7:0] a, b, input c-in, output c-out, output [7:0] wire c in4; Add rca 4 MO (a [3:0], b[3:0], c in, cin4, sum [3:0]) Add rca 4 M1 (a[7:4], b[7:4], c in4, c out, sum[7:4]); endmodule

Answer 1

module Add_half (
input a, b,
output c_out, sum
);

xor G1 (sum, a, b);
and G2 (c_out, a, b);

endmodule

module Add_full (
input a, b, c_in,
output c_out, sum
);

wire w1, w2, w3, w4;

Add_half M1 (a, b, w1, w2);
Add_half M2 (w2, c_in, w3, sum);
or O1 (c_out, w1, w3);

endmodule

module Adder_subtractor (
input [3:0] a, b, // A and B input
input M, // mode input
output [3:0] sum,
output c_out
);

wire [3:0] x;
wire c1, c2, c3;

xor G0 (x[0], b[0], M);
xor G1 (x[1], b[1], M);
xor G2 (x[2], b[2], M);
xor G3 (x[3], b[3], M);

Add_full m0 (.a(a[0]), .b(x[0]), .c_in(M), .sum(sum[0]), .c_out(c1));
Add_full m1 (.a(a[1]), .b(x[1]), .c_in(c1), .sum(sum[1]), .c_out(c2));
Add_full m2 (.a(a[2]), .b(x[2]), .c_in(c2), .sum(sum[2]), .c_out(c3));
Add_full m3 (.a(a[3]), .b(x[3]), .c_in(c3), .sum(sum[3]), .c_out(c_out));

endmodule

//TestBench

module top;
reg [3:0] a, b;
reg M;
wire [3:0] sum;
wire c_out;

integer i,j;

Adder_subtractor dut (.a(a), .b(b), .M(M), .c_out(c_out), .sum(sum));

initial begin
$monitor("a = %b b = %b M = %b c_out = %b sum = %b", a, b, M, c_out, sum);
M = 1'b0;
for (i = 5; i < 8 ; i = i + 1) begin
for (j = 6; j < 9 ; j = j + 1) begin
a = i; b = j; #20;
end
end

M = 1'b1;
for (i = 6; i < 8 ; i = i + 1) begin
for (j = 0; j < 5 ; j = j + 1) begin
a = i; b = j; #20;
end
end
end

endmodule

/******************* OUTPUT OF PROGRAM ********************

a = 0101 b = 0110 M = 0 c_out = 0 sum = 1011
a = 0101 b = 0111 M = 0 c_out = 0 sum = 1100
a = 0101 b = 1000 M = 0 c_out = 0 sum = 1101
a = 0110 b = 0110 M = 0 c_out = 0 sum = 1100
a = 0110 b = 0111 M = 0 c_out = 0 sum = 1101
a = 0110 b = 1000 M = 0 c_out = 0 sum = 1110
a = 0111 b = 0110 M = 0 c_out = 0 sum = 1101
a = 0111 b = 0111 M = 0 c_out = 0 sum = 1110
a = 0111 b = 1000 M = 0 c_out = 0 sum = 1111
a = 0110 b = 0000 M = 1 c_out = 1 sum = 0110
a = 0110 b = 0001 M = 1 c_out = 1 sum = 0101
a = 0110 b = 0010 M = 1 c_out = 1 sum = 0100
a = 0110 b = 0011 M = 1 c_out = 1 sum = 0011
a = 0110 b = 0100 M = 1 c_out = 1 sum = 0010
a = 0111 b = 0000 M = 1 c_out = 1 sum = 0111
a = 0111 b = 0001 M = 1 c_out = 1 sum = 0110
a = 0111 b = 0010 M = 1 c_out = 1 sum = 0101
a = 0111 b = 0011 M = 1 c_out = 1 sum = 0100
a = 0111 b = 0100 M = 1 c_out = 1 sum = 0011

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