Question

4. Design a 4-bit Adder / Subtractor. Follow the steps given below. (a) Write the VHDL code for a 1-bit Full Adder. The VHDL code must include an entity and an architecture. (b) Draw the circuit diagram for a 4-bit Adder / Subtractor. The circuit diagram may include the following logic elements: 1-bit Full Adders (shown as a block with inputs and outputs) Any 2-input logic gates Multiplexers Do not draw the logic circuit for the 1-bit Full Adder.

Answer 1

a) VHDL code for 1 bit full adder:-

library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);
end full_adder;
  
architecture dataf of full_adder is
begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end dataf;

b)

By A Az B, AO FULL ADOBR FULL ADDBA full ADDRD COROLL MODER sha cout Ha SS

If the value of K (Control line) is 1, th output of B0(xor)K=B0′(Complement B0). Thus the operation would be A+(B0′). Now 2’s complement subtraction for two numbers A and B is given by A+B’. This suggests that when K=1, the operation being performed on the four bit numbers is subtraction.

Similarly If the Value of K=0, B0 (xor) K=B0. The operation is A+B which is simple binary addition. This suggests that When K=0, the operation being performed on the four bit numbers is addition.

Then C0 is serially passed to the second full adder as one of it’s outputs.The sum/difference S0 is recorded as the least significant bit of the sum/difference. A1, A2, A3 are direct inputs to the second, third and fourth full adders.Then the third input is the B1, B2, B3 XORed with K to the second, third and fourth full adder respectively. The carry C1, C2 are serially passed to the successive full adder as one of the inputs. C3 becomes the total carry to the sum/difference. S1, S2, S3 are recorded to form the result with S0.