Question

Introduction: This experiment studies the design of an 8-bit adder/subtractor circuit using VHDL capture. The experiment investigates the implementation of addition and subtraction operations with circuits. This lab uses the virtual simulation environment to validate the design practically in the FPGA board. Equipment: • This experiment requires Quartus Prime and the Intel's DE2-115 FPGA board. • All students should have the Intel QP and ModelSim-Intel-Starter-Edition softwares installed in personal computers. • VPN connection to UNB Network and remote desktop software to remotely log into the assigned computer. Preparation: 1. Create a QP project with VHDL capture to implement the modified one-bit full adder/subtractor building block shown in Fig. 5-1 below (XOR gate to complement Y included in the 1-bit adder). This building block will be used to build an adder/subtractor with multiple bits. 2. Propose a set of test values to be used to verify the full 8-bit adder/subtractor operation. This should include values to test functionality for both addition Fig. 1 Full Adder/Subtractor Circuit. and subtraction using both unsigned integer and 2's complement signed integer. Your set should have at least 4 pairs of numbers for which you know the expected answer of the operation. Two duets of (X,Y) should be in lºs complement number representation (operation 1: X + Y, both positive numbers, operation 2: X+-Y), X positive and Y negative number). The other two duets should be made of signed 2's complement representation (operation 1: X+Y, both positive numbers and operation 2: X+-Y), X positive and Y negative number). The values of X and Y must be greater than 2010. Deliverables to upload in the D2L preparation dropbox: 1. A PDF file with the following information: a. A screen shot of your VHDL design file. b. A screen shot of your simulation window. You must test the 4 duets in l's and 2's complement c. The hand calculation of the 4 testing numbers performing the required operations.

Answer 1

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