Question

Write an Verilog code for a 8-bit subtractor (Bits are in 1's complement) using the following:

1. 5-bit parallel adder

2. 3-bit parallel adder

The condition are as follows:

1. The Most Significant bits of the subtractor must be given to the 5-bit parallel adder.

2, The Least Significant bits of the subtractor must be given to the 3-bit parallel adder.

3. The input A will be assign to the switches with the least significant bit A[0] linked to SW0. Similarly A[1] should be linked to SW1 , A[2] to SW2 and so on.

4. The input B will be assign to the switches with the least significant bit B[0] linked to SW8, Similarly B[1] should be linked to SW9, B[2] to SW10 and so on.

5. The output S will be assign to the LEDs with the least significant bit S[0] linked to LD0, Similarly S[1] should be linked to LD1, S[2] to LD2 and so on.

6. LD15 will be used to represent the carry bit of final output S.

7. The addition and subtraction operators (+,-) are not allowed in the codes.

Answer 1

one bit adder:

module adder_1bit(a,b,cin,sum,cy);
input a,b,cin;
output wire sum,cy;
assign sum= a ^ b ^ cin;
assign cy= (a &( b))|(cin&(a^(b)));
endmodule

Here by one bit module instantiations the 3 bit and 5 bit adders are designed .

3_bit adder:

module adder_3bit(a,b,cin,sum,cy);
input [2:0]a,b;
input cin;
output [2:0] sum;
output cy;
wire c0,c1;
adder_1bit z1(a[0],b[0],cin,sum[0],c0);
adder_1bit z2(a[1],b[1],c0,sum[1],c1);
adder_1bit z3(a[2],b[2],c1,sum[2],cy);
endmodule

5_bit adder:

module adder_5bit(a,b,cin,sum,cy);
input [4:0]a,b;
input cin;
output [4:0] sum;
output cy;
wire [3:0]c;
adder_1bit zz2(a[0],b[0],cin,sum[0],c[0]);
adder_1bit zz3(a[1],b[1],c[0],sum[1],c[1]);
adder_1bit zz4(a[2],b[2],c[1],sum[2],c[2]);
adder_1bit zz5(a[3],b[3],c[2],sum[3],c[3]);
adder_1bit zz6(a[4],b[4],c[3],sum[4],cy);

endmodule

The 8 bit substractor is designed by module instantiation of 3 bit and 5 bit adder.

8-bit substractor:

module substractor(a,b,s,cy,SW1,SW2,SW3,SW4,SW5,SW6,SW7,SW8,SW9,SW10,SW11,SW12,SW13,SW14,SW15,SW16,LD0,LD1,LD2,LD3,LD4,LD5,LD6,LD7,LD15);
input wire [7:0]a,b;
output [7:0]s;
output cy;
output wire LD15;
assign a[0]=1;
input wire SW1,SW2,SW3,SW4,SW5,SW6,SW7,SW8,SW9,SW10,SW11,SW12,SW13,SW14,SW15,SW16;
output wire LD0,LD1,LD2,LD3,LD4,LD5,LD6,LD7;
wire c0,c1;
wire [7:0]b1;
assign SW1=a[0],SW2=a[1],SW3=a[2],SW4=a[3],SW5=a[4],SW6=a[5],SW7=a[6],SW8=a[7];
assign SW9=b[0],SW10=b[1],SW11=b[2],SW12=b[3],SW13=b[4],SW14=b[5],SW15=b[6],SW16=b[7];
assign b1=~b;
adder_3bit zzz2(a[2:0],b1[2:0],1,s[2:0],c0);   
adder_5bit zzz1(a[7:3],b1[7:3],c0,s[7:3],c1);
assign LD0=s[0],LD1=s[1],LD2=s[2],LD3=s[3],LD4=s[4],LD5=s[5],LD6=s[6],LD7=s[7];
assign cy=~c1;
assign LD15=cy;
endmodule

The output :