Building and testing basic combinational circuits using Verilog HDL
Description: Build and test the following circuits using gate-level modeling in Verilog HDL.
1. 3-input majority function.
2. Conditional inverter (see the table below: x - control input, y - data input). Do NOT use XOR gates for the implementation.
x | y | Output |
0 | y | |
1 | y' |
3. Two-input multiplexer (see the table below: x,y - data inputs, z - control input).
z | Output |
0 | x |
1 | y |
4. 1-bit half adder.
5. 1-bit full adder by cascading two half adders.
6. 1-bit full adder directly (as in fig. 4.7 in the text).
7. 4-bit adder/subtractor with overflow detection by cascading four 1-bit full adders (see fig. 4.13 in the text).
Requirements:
Extra: Implement an ABCD-to-seven-segment decoder with the modification that the six invalid combinations of the input should be used as don't care conditions. Reuse components if possible to minimize the circuit. Test the circuit with all decimal digits. Include in the report the maps for all functions, the gate level diagrams, and the Verilog code and test results.
1.
INPUTs |
OUTPUT |
||
A |
B |
C |
F |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
module majority_function (A, B, C, F);
input A, B, C;
output F;
assign F = (A & B) | (B & C) | (A & C);
endmodule
////////////////////////////////////////////////////////////////////////
2.
module conditional_inverter (X, Y, F);
input X, Y;
output F;
assign F = X ? ~Y : Y;
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////////////
3
module multiplexer_2_1 (X, Y, Z, F);
input X, Y, Z;
output F;
assign F = Z ? Y : X;
endmodule
4
module half_adder (X, Y, SUM, CARRY);
input X, Y;
output SUM, CARRY;
assign SUM = X ^ Y;
assign CARRY = X & Y;
endmodule
Building and testing basic combinational circuits using Verilog HDL Description: Build and test t...
Building and testing basic combinational circuits using Verilog HDL Description: Build and test the following circuits using gate-level modeling in Verilog HDL 1.3-input majority function 2.Conditional inverter (see the table below: x - control input, y -data input). Do NOT use XOR gates for the implementation. Output 3. Two-input multiplexer (see the table below: x.y -data inputs, z- control input) Output 4. 1-bit half adder. 5. 1-bit full adder by cascading two half adders 6.1-bit full adder directly (as in...
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