Question

FPGA (Interconnected Adder Modules)

In this lab you will implement adder circuits using data flow modelling. You will also create 3-bit adder by employing interconnected 1-bit full adders.

1. Data flow modelling of a 1-bit full adder circuit.
2. Data flow modelling of a 3-bit adder circuit. There will be 7 inputs (X2, X1, X0, Y2, Y1, YO, Cin) - please put them in that order - Switch 6 will represent X2 and Switch 0 will be the Cin. There should be 4 outputs (Cout, S2, S1, SO) LED3 will represent Cout and LED0 will represent SO. For this circuit you should employ instances of the data flow version of 1-bit full adder module above. Your inputs X and Y should be 3-bit buses. Your Sum outputs should be a 4-bit bus.
3. Deliverable: Get a printout of your Verilog source code for the 3-bit adder circuit and the 1-bit full adder. Demo your 3-bit full adder circuit to your lab instructor and have your lab instructor initial your printout.

Answer 1

1 Bit full adder:

Data flow modeling implies a boolean equation for the out puts with respective to inputs.

Boolean equation is obtained from the truth table.

Truth table for 1 bit full adder, let a,b be two input, for full adder c will be third input and s,Co will be two outputs.

a b c s Co

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0   1 0

1 0 1 0 1

1 1 0 0 1

1 1 1   1 1

Boolean equation using K map : s = a^b^c

Co = (a&b)|(b&c)|(c&a)

Со

3 bit full adder using 1 bit full adder:

X2 X1 X0

   + Y2 Y1 Y0

S3 S2 S1 S0

We implement 3 bit fulladder similar to the general addition using 1 bit full adder.

y2 x2 yo xD Cin co s S3 S2

Carry out of 1st Fulladder is connected to Carry in of 2nd fulladder module. similarly others and final Cout is S3.

Verilog code:

module FA_1bit ( input a,b,c, output s,Co);

assign s = a^b^c;

assign Co = (a&b)|(b&c)|(c&a);

end module

module FA_3bit ( input X[0], X[1], X[2], Y[0], Y[1], Y[2], Cin, output [3:0]S );

wire L,M;

FA_1bit FA1 ( X[0], Y[0], Cin, S[0], L);   

FA_1bit FA2 ( X[1], Y[1], L, S[1], M); // module instantiation positional.

FA_1bit FA3 ( X[2], Y[2], M, S[2], S[3]); // FA_1bit is module we used it multiple times to make  FA_3bit.

end module

7 switches are 7inputs connected in serial order. S output is connected to 4 LEDs.

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