Question

DOING NUMBER 7 of VHDL lab "write your own full-adder in VHDL " is my only request. Do the rest, if you have time.

To verify and apply techniques to build half adders and full adder to perform additions using gates. For each part of the procedure, show the number of that section and include a logic diagram of the circuit, truth table for the circuit, and any other necessary information. Adder Implementation 1. Construct a binary half-adder and record the truth table for this circuit. A. 2. Using the two half adder blocks you have built above and an OR gate, build a Full adder that has Cin. Provide complete schematic and record the truth table for this full adder

Answer 1

ENTITY full_adder Is PORT (A, B, C_in: IN BIT: S, COUT: OUT BIT): END full adder ARCHITECTURE full_adder_beh OF BEGIN PROCESS (A, B, C_in) VARIABLE t: BIT: BEGIN t = A XOR B: S < = t XOR C_in: C_out < = (A AND B) OR (t AND C_in): END PROCESS END full_adder_beh;