Question

need help please thanks!

Draw a gate-level schematic for the fall-adder module. XOR gates can be used to usplement Sotput; two levels ofNAND ples are handy for tn lema îngC, as a sum of products Create a MOSFET cirout for each of the logic gates you used in step 1 Your lab assigment this week is to design and test a CMOS circuit that performs addition Some suggestions on how to proceed Let's start with a simple ripple-cany adder based on the full-adder modale discsed in lecture the Beta (the computer central processing unit we'll be designing in later labs) The fall adder module has 3 inpats (A. B and C) and 2 outpats (S and C). The logis equations ndtruth table for sand C, are own below 0 01 1 0 0 10 10 1 0010 Typically S is implemented using two cascaded 2-input XOR gates. One can use three 2-input NANDs and one S-int NAND to implement C(remember that by Demorgan's Law two cascaded NANDs is logically equivalent to a cascade of AND OR) The module parforms the addition of two one-bit inputs (A and B) incorponating the carry in from the previons stage (C). The resl appears on the S output and a cary (C) is generated for the nest stage. A possible schematic for the 4-bit adder is showm below FA FA FA FA S4 Sa Si So

Answer 1

Full Adder Sum S = A oplus B oplus C_in C_0 = AB + AC_in + BC_in \r\n Gate level schematic for full Adder S = A oplus B oplus C C_0 = (AB^-) (AC_in^-) (BC_in^-)^- C_0 = (AB^-) (AC_in^-) (BC_in^-)^- Using Demorgan's law = (AB^-) + (AC_in^-) + (BC_in^-) C_0 = AB + AC_in + BC_in MOSFET circuits for each of logic gates 2 - input NAND gate \r\n AC_in^-: - BC_in^- (AB^-)^- (BC_in^-)^- (AC_in^-)^-: - o/p = (AB^-) (AC_in^-) (BC_in^-)^- \r\n XOR Gate (AB^- + A^- B)