1st Method:
module dff(clk,reset,din,dout);
input clk,reset,din;
output dout;
logic dout;
always@(posedge
clk,negedge reset)
if(!reset)
dout <= 0;
else
dout <= din;
endmodule
module ones_counter(clk,reset,data,count);
input clk,reset,data;
output [0:3] count;
dff d1(clk,reset,data,count[0]);
dff d2(count[0],reset,~count[1],count[1]);
dff d3(count[1],reset,~count[2],count[2]);
dff d4(count[2],reset,~count[3],count[3]);
endmodule
2nd method:
module num_ones_for(
input [15:0] A,
output reg [4:0] ones
);
integer i;
always@(A)
begin
ones = 0; //initialize count variable.
for(i=0;i<16;i=i+1) //for all the
bits.
ones = ones + A[i]; //Add the bit to the count.
end
endmodule
Test Bench:
module tb;
// Inputs
reg [15:0] A;
// Outputs
wire [4:0] ones;
// Instantiate the Unit Under Test (UUT)
num_ones_for uut (
.A(A),
.ones(ones)
);
initial begin
A = 16'hFFFF; #100;
A = 16'hF56F; #100;
A = 16'h3FFF; #100;
A = 16'h0001; #100;
A = 16'hF10F; #100;
A = 16'h7822; #100;
A = 16'h7ABC; #100;
end
endmodule
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