Question

Write a behavioral Verilog module for a 4-bit Johnson counter that has 8 states. The counter loads the "0000" state if reset is low. The counter should start and end with this state. Write a testbench to verify the correctness of the 4-bit Johnson counter. The testbenclh should have a clock with a period of 20ns and a reset signal. The testbench should store the 4-bit binary outputs of the counter in a file, which will be used to provide an input data stream for the sequence detector. Write a behavioral Verilog module for the sequence detector. You can use either Mealy or Moore machine based on the description given for implementation. The circuit should have one output bit and three inputs: clock, reset, and an input bit Write a testbench to verify the correctness of the sequence detector. The testbench should have a clock with 20ns period and a reset signal. The testbench should read the 4-bit binary outputs of the counter from the file generated from the counter's testbench Then, these 4-bit binary words will be sent as one bit at a time to provide the input data stream for the sequence detector. The stream starts with the least significant bit (LSB) of the first word. Once the most significant bit of the first word is used, the LSB of the second word is used, and so on. The testbench should also store the input and output data in a text file.

Answer 1

Reha Viduyal Cade out , out i (neset) of d;

snd snd modzls test bench - 4b reg clik begin au4'bo000 fork s C end

module mealy_verilog_code(out, in, rst, clk);
output out;
input in;
input clk, rst;
reg out;
reg[1:0] state;
parameters0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0) begin state=s0; out=0; end
else begin
case (state)
s0: if(in==0) begin out=0; state=s1; end
else begin out=0; state=s0; end
s1: if(in==0) beginout=0; state=s1; end
else begin out=0; state=s2; end
s2: if(in==0) begin out=0; state=s3; end
else begin out=0; state=s0; end
s3: if(in==0) begin out=0; state=s1; end
else begin out=1; state=s2; end
default: state=s0;
endcase
end
endmodule

3-bit melay Ce».in. reid,nu ) moduし begin 孔Int End snd modulo