Question

write a module in verilog that takes in a 1 hz clock and outputs a counter for hours seconds and minutes on a digital clock. I was thinking of making two bits for hours minutes and seconds. when the first bit gets to 9, then it resets to 0 and the second bit, or most significant bit becomes 1. please do not paste the code online.....put it in a file I can simply test. privacy is important here

Answer 1

I am giving you the code to the upward counter in verilog and hope it will help you to implement it on the given code

module clk_counter (
op ,                
en ,                                            
clock_ip ,    
refresh   
);

output [7:0] op;                    // O/p ports

input en, clock_ip, refresh;        // I/p ports

reg [7:0] op;

   //Code starts
  
always @(posedge clock_ip)
if (refresh) begin
op <= 8'b0 ;
end else if (en) begin
op <= op + 1;
end

endmodule

Hope it helps.