Question

Objective: Creating a register file (memory) using Verilog. The register file is made up of four registers and each register holds one nibble (half a byte, i.e., four bits) 3. Create a D flip-flop AD flip-flop holds 1 bit of data, and it only changes its data when the clock changes. We want a positive edge triggered flip-flop. Design your Verilog D flip-flop, so we will create them now. Enter the 2 to 4 line decoder. We will need two decoders in the final step of our modifications. design Put D" first in the port list. As a general rule, outputs are always first The ports A" and B" are actually the address bits so combine them into one new port "A" that has two bits. Note you will have to change the port list, input line, and the assignments. Change the bit ordering of D" from "T0:3]"(big endian) to 3:01(little endian) to be consistent with the rest of the design Build the register file from the registers data in3:0 |data out[3:0] data in3:0 load data out[3:0 4-bit Reg out en write add data in[3:0 load data out[3:0 write en 4-bit Reg out en data in[3:0 load data out[3:0 2 4-bit Reg out en read add |dat a in3:0 load data out[3:0 read en 4-bit Reg out en register file, like the diagram shown above Create a module to hold our /name: Register_File // desc: 4x4 register file date / by module Register_File(data_out,data_in,read_add, read_en,write_add, write_en); input input input output [3:0] data_out; [3:0] data_in [1:0] read_add, write_add; // read address and write address /data to write /read and write enable read_en,write_en; /data to read wire [3:0] read_sel,write_sel; //instantiate registers here dec2x4 Dec_Read (read_sel, read_en, read_add) dec2x4 Dec_Write (write_sel, write_en, write_add) //instantiate registers here Nibble_Reg Reg_®(data_out, data_in,write_sel[0], read_sel[0]); / finish making instances endmodule

Answer 1

Answer 1)

//Register File
// First we are developing the 2 to 4 decoder

module dec2x4 (out1, enable, select);
input enable;
input [1:0] select;
output [3:0] out1;
reg [3:0] out1;

always @(enable, select)
begin
if (enable)
begin
case(select)
2'b00 : out1 = 4'b0001;
2'b01 : out1 = 4'b0010;
2'b10 : out1 = 4'b0100;
2'b11 : out1 = 4'b1000;
endcase
end
else
begin
out1 = 4'b0000;
end
end
  
endmodule

// The module for D flip flop is below

module DFF (Q, clk, D);
input clk;
input D;
output reg Q;

always @ (posedge clk)
begin
Q <= D;
end

endmodule

// We are now developing the 4 bit register to store the data based on load input

// and will give the output only on output enable (out_en)

module Nibble_reg (data_out, clk, data_in, load, out_en);
input clk;
input [3:0] data_in;
input load;
input out_en;
output [3:0] data_out;

wire [3:0] data_i, data_o;

// instantiate D flip flops here
DFF dff_0 (.clk(clk), .D(data_i[0]), .Q(data_o[0]));
DFF dff_1 (.clk(clk), .D(data_i[1]), .Q(data_o[1]));
DFF dff_2 (.clk(clk), .D(data_i[2]), .Q(data_o[2]));
DFF dff_3 (.clk(clk), .D(data_i[3]), .Q(data_o[3]));

assign data_i = load ? data_in : 4'd0;
assign data_o = out_en ? data_o : 4'd0;

endmodule

// The Top level for the register file is mentioned below
module Register_File(data_out, clk, data_in, read_add, read_en, write_add, write_en);
input clk;
input [3:0] data_in;
input [1:0] read_add, write_add;
input read_en, write_en;
output [3:0] data_out;

wire [3:0] read_sel, write_sel;

// instantiate decoders here

dec2x4 Dec_Read (read_sel, read_en, read_add);
dec2x4 Dec_Write (write_sel, write_en, write_add);

// instantiate registers here
Nibble_reg Reg_0 (data_out, clk, data_in, write_sel[0], read_sel[0]);
Nibble_reg Reg_1 (data_out, clk, data_in, write_sel[1], read_sel[1]);
Nibble_reg Reg_2 (data_out, clk, data_in, write_sel[2], read_sel[2]);
Nibble_reg Reg_3 (data_out, clk, data_in, write_sel[3], read_sel[3]);

endmodule