Question

Register File

Consider the following register file, that provide one write port and two read ports. A register is updated on the positive edge on the clock if dw=1. Data is written to rd. The two read ports are: rn and rm.

typedef logic [15:0] reg16_t;
typedef logic [2:0] reg_sel_t;

module reg_file(
    output reg16_t rn, rm, input reg16_t rd,
    input reg_sel_t n, m, d,
    input logic dw, reset, clk
);

Use behavioural Verilog to implement reg_file.

module reg_file(
output reg16_t rn, rm, input reg16_t rd,
input reg_sel_t n, m, d,
input logic dw, reset, clk
);

endmodule

Answer 1

module reg_ file(

output reg16_ t rn,rm,input reg16_t Rd,

input reg_sel_t n,m,d

input ligic dw,reset,clk

);