Question

EEL4768C Lab Assignment 6 (40 points) Due 7/24/2018, 11:59 pm on Canvas Register file is an important state element of the MIPS processor. Consider the register file shown below. The register file can read and write the data into the registers. The register file has two read ports (A1, A2) and one write port (A3). The width of Al, A2 and A3 is 5 bits. Writing data into the register is synchronized with the clock signal. WE is the write enable control signal. WD contains the data for the write operation Implement the register file in VHDL/Verilog. CLK A1 A2 RD2 3 ?? WD3 Register

Answer 1

module register_file (input [4:0] A1, A2, A3, input [31:0] WD3,
output reg [31:0] RD1, RD2,
input CLK, input WE3);

// register is the memory with 32 Different address and width size is also 32
reg [31:0] register [0:31];

// Reading data with corresponding read address A1 and A2
always @(posedge CLK) begin
RD1 <= register[A1];

RD2 <= register[A2];
end

// Writting Data to register number A3 with WE3 = 1 and WD3 = valid write data
always @ (posedge CLK) begin
if (WE3) register[A3] <= WD3;
end