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Problem: Design a clocked synchronous state machine with two inputs A, and B, and a single output Z that is 1 is: .A had the same value at each of the two previous clock ticks, or B has been 1 since the last time that the first condition was true. In-Lab 1. 2. 3. 4. For the finite state machine (FSM), identify the minimum number of states required Draw the state transition diagram Complete the state transition table Derive the logic equations from table in step-3, and write a Verilog code for the FSM with the following parameters a. File name b. Module name c. Input port d. Output port fsm part 1_lab_02.v fsm part 1_lab 02 A, B, RESET, CLK 5. Verify the functionality designed in step-4 using the testbench provided. 6. Using the state transition diagram in step-2 and case statements, write a Verilog code for the FSM with the following parameters a. File name b. Module name c. Input port d. Output port fsm part 2_lab_02.v fsm part 2_lab_02 A, B, RESET, CLK 7. Verify the functionality designed in step-6 using the testbench provided.

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