Question

4) Finite State Machine (FSM) Write a System Verilog module using always_ff and always_comb that implements the Finite machine in this state table. Use good code organization and indentation for full credit. State Transition Table State Assignment State Q3Q2Q1Q Present Next State State x-1 0001 0010 0100 1000 a) This state assignment indicates we are using what type of coding Which model of Finite State Machine is this, Mealy or Moore, Write the System Verilog code for the module statement and declarations, and use localparams for the b) states c) Write the System Verilog code for the synchronous part of this code d) Write the System Verilog code for the combinatorial part of this code

Answer 1

4- en Coda ,8 ~FF @CPositive. edg.. 1k) toeset) begin

end ebe se. end end Cobe Ccusent.sa ) ή:ぱ(X) begin next-state ←A,, end else beaun end end eye begin

end c:甘(x) begin end else begin end D:) begin end ese begin end daboutbeqin enal en d end vuodul