Question

Timescale is set to 100 ps / 1ps and the 1-bit signal of both inputs A and B is (0,0) -> (0,1) -> (1,0) -> (1,1 ) To simulate the output waveform of each logic when input to the AND, OR, NAND, NOR, and XOR logic with two inputs. Please submit the following for your design logic:

(1) Verilog code (basic.v).

(2) Testbench code (tb1.v)

(3) Execute (1) in ModelSim to output the waveform

◼ Define a module with the name of basic in basic.v, input A and

B to receive input, and define output port to output out_AND, out_OR, out_NAND, out_NOR, out_XOR. (The port name is an example, and can be arbitrarily named for its meaning)

◼ testbench calls the basic module defined in basic.v, connects the input and output, and inputs the input in the given time unit and value. After that, we simulate the input and output waveforms and check whether the output of the logic such as AND, OR, etc. is correctly output.

◼ Logic and testbench are designed on different files.

Answer 1

//basic.v

//verilog code for basic AND,OR,NAND.NOR,EXOR gates

module basic (

//I/o DECLARATIONS

input A,

input B,

output out_AND,

output out_OR,

output out_NAND,

output out_NOR,

output out_XOR

);

//AND logic

assign out_AND = (A && B );

//OR logic

assign out_OR = (A || B);

//NAND logic

assign out_NAND = (~(A && B));

//NOR logic

assign out_NOR = (~(A || B));

//XOR logic

assign out_XOR = (A ^ B);

endmodule

//tb1.v

//verilog testbench code for basic gates

module test_basic;

reg A;

reg B;

wire out_AND;

wire out_OR;

wire out_NAND;

wire out_NOR;

wire out_XOR;

//instantiate unit under test(UUT)

basic UUT (A,B,out_AND,out_OR,out_NAND,out_NOR,out_XOR);

initial begin

A= 0;B=0;#10;

A= 0;B=1;#10;

A= 1;B=0;#10;

A= 1;B=1;

#10 $finish;

end

endmodule

// Simulation waveforms