ZuoTi.Pro
Question

– Write and test a constrained random stimulus testcase for the testbench. Use ModelSim or a simi...

– Write and test a constrained random stimulus testcase for the testbench. Use ModelSim or a similar simulator to test the transactor. Provide the code and evidence of its function.

// ----------------------------------------------------------------------------
// File name: alu.v
// Designed by: Jim Moran
// ----------------------------------------------------------------------------
//
// This module is the Arithmetic Logic Unit
//
// ----------------------------------------------------------------------------

`timescale 1ns/1ps

//-----------------------------------------------------------------------------
// Module Declaration
//-----------------------------------------------------------------------------
module alu (
   // Global Signals
   Clk_In, // Rising Edge Clock Input
   Rst_l_In, // Active Low Reset Input
   // Operation Interface
   Operation_In, // Operation Select Input
   // Data Bus Interface
   Bus_A_In, // Data Bus A Input
   Bus_B_In, // Data Bus B Input
   Bus_Out, // Data Bus Output
// Error Interface
   Error_Out // Error Output
   );

//-----------------------------------------------------------------------------
// Parameters
//-----------------------------------------------------------------------------
parameter BUS_WIDTH = 32;
parameter Oper_Invert = 3'b000;
parameter Oper_And = 3'b001;
parameter Oper_Or = 3'b010;
parameter Oper_Xor = 3'b011;
parameter Oper_Zero = 3'b100;
parameter Oper_Comp = 3'b101;
parameter Oper_Add = 3'b110;
parameter Oper_Sub = 3'b111;

//-----------------------------------------------------------------------------
// IO Declarations
//-----------------------------------------------------------------------------
// Global Signals
input Clk_In; // Rising Edge Clock Input
input Rst_l_In; // Active Low Reset Input
// Operation Interface
input [2:0] Operation_In; // Operation Select Input
// Data Bus Interface
input [BUS_WIDTH - 1:0] Bus_A_In; // Data Bus A Input
input [BUS_WIDTH - 1:0] Bus_B_In; // Data Bus B Input
output [BUS_WIDTH - 1:0] Bus_Out; // Data Bus Output
// Error Interface
output        Error_Out; // Error Output

//-----------------------------------------------------------------------------
// Output Registers
//-----------------------------------------------------------------------------
reg [BUS_WIDTH - 1:0] Bus_Out; // Data Bus Register
reg            Error_Out; // Error Register

//-----------------------------------------------------------------------------
// Internal Registers and Wires
//-----------------------------------------------------------------------------
wire [BUS_WIDTH : 0] Sum_Temp; // Intermediate Sum
wire [BUS_WIDTH : 0] Diff_Temp; // Intermediate Difference

//-----------------------------------------------------------------------------
// Assigns
//-----------------------------------------------------------------------------
assign Sum_Temp = {Bus_A_In[BUS_WIDTH - 1],Bus_A_In} + {Bus_B_In[BUS_WIDTH - 1],Bus_B_In};
assign Diff_Temp = {Bus_A_In[BUS_WIDTH - 1],Bus_A_In} - {Bus_B_In[BUS_WIDTH - 1],Bus_B_In};

//-----------------------------------------------------------------------------
// Instantiations
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// RTL
//-----------------------------------------------------------------------------

always @ (posedge Clk_In or negedge Rst_l_In) begin
if (~Rst_l_In) begin
Bus_Out <= {BUS_WIDTH{1'b0}};
   Error_Out <= 1'b0;
end
else begin
   case (Operation_In)
   Oper_Invert: begin
   Bus_Out <= !Bus_A_In;
   Error_Out <= 1'b0;
   end
   Oper_And: begin
   Bus_Out <= Bus_A_In & Bus_B_In;
   Error_Out <= 1'b0;
   end
   Oper_Or: begin
   Bus_Out <= Bus_A_In | Bus_B_In;
   Error_Out <= 1'b0;
   end
   Oper_Xor: begin
    Bus_Out <= Bus_A_In ^ Bus_B_In;
   Error_Out <= 1'b0;
   end
   Oper_Zero: begin
Bus_Out <= {BUS_WIDTH{1'b0}};
   Error_Out <= 1'b0;
   end
   Oper_Comp: begin
Bus_Out <= {BUS_WIDTH{1'b0}} - Bus_A_In;
   Error_Out <= 1'b0;
   end
   Oper_Add: begin
   if ((Sum_Temp[BUS_WIDTH] && Bus_A_In[BUS_WIDTH - 1] && Bus_B_In[BUS_WIDTH - 1]) |
       (~Sum_Temp[BUS_WIDTH] && ~Bus_A_In[BUS_WIDTH - 1] && ~Bus_B_In[BUS_WIDTH - 1])) begin
       Bus_Out <= Sum_Temp[BUS_WIDTH - 1:0];
        Error_Out <= 1'b0;
   end
   else begin
       Bus_Out <= {BUS_WIDTH{1'b0}};
       Error_Out <= 1'b1;
   end
   end
   Oper_Sub: begin
   if ((Diff_Temp[BUS_WIDTH] && Bus_A_In[BUS_WIDTH - 1] && Bus_B_In[BUS_WIDTH - 1]) |
       (~Diff_Temp[BUS_WIDTH] && ~Bus_A_In[BUS_WIDTH - 1] && ~Bus_B_In[BUS_WIDTH - 1])) begin
       Bus_Out <= Diff_Temp[BUS_WIDTH - 1:0];
       Error_Out <= 1'b0;
   end
   else begin
       Bus_Out <= {BUS_WIDTH{1'b0}};
       Error_Out <= 1'b1;
   end

   end
   default: begin
Bus_Out <= {BUS_WIDTH{1'b0}};
   Error_Out <= 1'b0;
   end
   endcase
end
end  
endmodule // alu

engineering   Electrical-Engineering   
0 0
Add a comment Improve this question Transcribed image text
Next > < Previous
Sort answers by oldest

Homework Answers

Answer #1

// verilog design foe alu
// File name: alu.v
// Designed by: Jim Moran
// ----------------------------------------------------------------------------
//
// This module is the Arithmetic Logic Unit
//
// ----------------------------------------------------------------------------

`timescale 1ns/1ps

//-----------------------------------------------------------------------------
// Module Declaration
//-----------------------------------------------------------------------------
module alu (
// Global Signals
Clk_In, // Rising Edge Clock Input
Rst_l_In, // Active Low Reset Input
// Operation Interface
Operation_In, // Operation Select Input
// Data Bus Interface
Bus_A_In, // Data Bus A Input
Bus_B_In, // Data Bus B Input
Bus_Out, // Data Bus Output
// Error Interface
Error_Out // Error Output
);

//-----------------------------------------------------------------------------
// Parameters
//-----------------------------------------------------------------------------
parameter BUS_WIDTH = 32;
parameter Oper_Invert = 3'b000;
parameter Oper_And = 3'b001;
parameter Oper_Or = 3'b010;
parameter Oper_Xor = 3'b011;
parameter Oper_Zero = 3'b100;
parameter Oper_Comp = 3'b101;
parameter Oper_Add = 3'b110;
parameter Oper_Sub = 3'b111;

//-----------------------------------------------------------------------------
// IO Declarations
//-----------------------------------------------------------------------------
// Global Signals
input Clk_In; // Rising Edge Clock Input
input Rst_l_In; // Active Low Reset Input
// Operation Interface
input [2:0] Operation_In; // Operation Select Input
// Data Bus Interface
input [BUS_WIDTH - 1:0] Bus_A_In; // Data Bus A Input
input [BUS_WIDTH - 1:0] Bus_B_In; // Data Bus B Input
output [BUS_WIDTH - 1:0] Bus_Out; // Data Bus Output
// Error Interface
output Error_Out; // Error Output

//-----------------------------------------------------------------------------
// Output Registers
//-----------------------------------------------------------------------------
reg [BUS_WIDTH - 1:0] Bus_Out; // Data Bus Register
reg Error_Out; // Error Register

//-----------------------------------------------------------------------------
// Internal Registers and Wires
//-----------------------------------------------------------------------------
wire [BUS_WIDTH : 0] Sum_Temp; // Intermediate Sum
wire [BUS_WIDTH : 0] Diff_Temp; // Intermediate Difference

//-----------------------------------------------------------------------------
// Assigns
//-----------------------------------------------------------------------------
assign Sum_Temp = {Bus_A_In[BUS_WIDTH - 1],Bus_A_In} + {Bus_B_In[BUS_WIDTH - 1],Bus_B_In};
assign Diff_Temp = {Bus_A_In[BUS_WIDTH - 1],Bus_A_In} - {Bus_B_In[BUS_WIDTH - 1],Bus_B_In};

//-----------------------------------------------------------------------------
// Instantiations
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// RTL
//-----------------------------------------------------------------------------

always @ (posedge Clk_In or negedge Rst_l_In) begin
if (~Rst_l_In) begin
Bus_Out <= {BUS_WIDTH{1'b0}};
Error_Out <= 1'b0;
end
else begin
case (Operation_In)
Oper_Invert: begin
Bus_Out <= !Bus_A_In;
Error_Out <= 1'b0;
end
Oper_And: begin
Bus_Out <= Bus_A_In & Bus_B_In;
Error_Out <= 1'b0;
end
Oper_Or: begin
Bus_Out <= Bus_A_In | Bus_B_In;
Error_Out <= 1'b0;
end
Oper_Xor: begin
Bus_Out <= Bus_A_In ^ Bus_B_In;
Error_Out <= 1'b0;
end
Oper_Zero: begin
Bus_Out <= {BUS_WIDTH{1'b0}};
Error_Out <= 1'b0;
end
Oper_Comp: begin
Bus_Out <= {BUS_WIDTH{1'b0}} - Bus_A_In;
Error_Out <= 1'b0;
end
Oper_Add: begin
if ((Sum_Temp[BUS_WIDTH] && Bus_A_In[BUS_WIDTH - 1] && Bus_B_In[BUS_WIDTH - 1]) |
(~Sum_Temp[BUS_WIDTH] && ~Bus_A_In[BUS_WIDTH - 1] && ~Bus_B_In[BUS_WIDTH - 1])) begin
Bus_Out <= Sum_Temp[BUS_WIDTH - 1:0];
Error_Out <= 1'b0;
end
else begin
Bus_Out <= {BUS_WIDTH{1'b0}};
Error_Out <= 1'b1;
end
end
Oper_Sub: begin
if ((Diff_Temp[BUS_WIDTH] && Bus_A_In[BUS_WIDTH - 1] && Bus_B_In[BUS_WIDTH - 1]) |
(~Diff_Temp[BUS_WIDTH] && ~Bus_A_In[BUS_WIDTH - 1] && ~Bus_B_In[BUS_WIDTH - 1])) begin
Bus_Out <= Diff_Temp[BUS_WIDTH - 1:0];
Error_Out <= 1'b0;
end
else begin
Bus_Out <= {BUS_WIDTH{1'b0}};
Error_Out <= 1'b1;
end

end
default: begin
Bus_Out <= {BUS_WIDTH{1'b0}};
Error_Out <= 1'b0;
end
endcase
end
end  
endmodule // alu

// verilog testbench for given alu
module test_alu;
  
// Parameters
//-----------------------------------------------------------------------------
parameter BUS_WIDTH = 32;
parameter Oper_Invert = 3'b000;
parameter Oper_And = 3'b001;
parameter Oper_Or = 3'b010;
parameter Oper_Xor = 3'b011;
parameter Oper_Zero = 3'b100;
parameter Oper_Comp = 3'b101;
parameter Oper_Add = 3'b110;
parameter Oper_Sub = 3'b111;
  
// Global Signals
reg Clk_In; // Rising Edge Clock Input
reg Rst_1_In; // Active Low Reset Input
// Operation Interface
reg [2:0] Operation_In; // Operation Select Input
// Data Bus Interface
reg [BUS_WIDTH - 1:0] Bus_A_In; // Data Bus A Input
reg [BUS_WIDTH - 1:0] Bus_B_In; // Data Bus B Input
wire [BUS_WIDTH - 1:0] Bus_Out; // Data Bus Output
// Error Interface
wire Error_Out; // Error Output
  

// instantiation of device under test
alu DUT (Clk_In,Rst_1_In, Operation_In,Bus_A_In,Bus_B_In,Bus_Out,Error_Out);
  
initial begin
$dumpfile ("dump.vcd");
$dumpvars;
Clk_In=0;
forever #5 Clk_In = ! Clk_In;
end
  
  
initial begin
Rst_1_In = 1'b0;
#20 Rst_1_In = 1'b1;
end
  
initial begin
repeat(10)
@(negedge Clk_In) begin
Operation_In = $random;
Bus_A_In = $random;
Bus_B_In = $random;
end
$finish ;
end
  
  
endmodule
  

// Simulation waveforms

From: Ops To: 100,000ps Get Signals | Radix, a 100% 44 » 60 20,00 Bus A In31:0 XXXX XXXX 089 581b9.7bod3937 5212 3b23 116 462

0 0
Add a comment
Know the answer?
Add Answer to:
– Write and test a constrained random stimulus testcase for the testbench. Use ModelSim or a simi...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions

  • Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code...

    Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code Simulate the circuit using ISim and analyze the resulting waveform. Verilog Code for dff_fe_asyn_h is mentioned below:- //DFF module with asynchronous active high reset with negative edge trigger with clock module dff_fe_asyn_h ( input clock, // Clock Input input reset, // Reset Input input data_in, // Input Data output reg data_out // Output Data ); always @ (negedge clock or posedge reset) // triggers...

  • Write a testbench for use in Quartus' ModelSim Altera in verilog for the following code of...

    Write a testbench for use in Quartus' ModelSim Altera in verilog for the following code of a 4x16 register: module regFile4x16 (input clk, input write, input [2:0] wrAddr, input [15:0] wrData, input [2:0] rdAddrA, output [15:0] rdDataA, input [2:0] rdAddrB, output [15:0] rdDataB); reg [15:0]    reg0, reg1, reg2, reg3; assign rdDataA = rdAddrA == 0 ? reg0 :        rdAddrA == 1 ? reg1 :        rdAddrA == 2 ? reg2 :        rdAddrA == 3...

  • I need help writing a test bench for the following Verilog code module CU(IE, WE, WA,...

    I need help writing a test bench for the following Verilog code module CU(IE, WE, WA, RAE, RAA, RBE, RBA, ALU,                SH, OE, start, clk, reset, Ng5); //nG5 denotes (N>5);    input start, clk, reset;    output IE, WE, RAE, RBE, OE;    output [1:0] WA, RAA, RBA, SH;    output [2:0] ALU;       input wire Ng5;    reg [1:0] state;    reg [1:0] nextstate;    parameter S0 = 3'b000;    parameter S1 = 3'b001;...

  • a Read the following codes in Verilog and the corresponding testbench file. Describe what the codes...

    a Read the following codes in Verilog and the corresponding testbench file. Describe what the codes are doing by adding comments in the code. Then write down the simulation results of res1, res2, res3, and res4, respectively. Source code module vector_defn (num1, res1, res2, res3, res4); input [7:0] num1; output res1; output [3:0] res2; output [0:7] res3; output [15:0] res4; assign res1=num1[2]; assign res2=num1[7:4]; assign res3=num1; assign res4={2{num1}}; endmodule testbench: `timescale 1ns / 1ps module vector_defn_tb; reg [7:0] in1; wire...

  • Modify the Moore FSM below to detect the sequence "110" , simulate using the same test...

    Modify the Moore FSM below to detect the sequence "110" , simulate using the same test bench and create a Moore Transition Diagram for the new sequence 110. module moore_seq (    input clock, reset, x,    output reg z ); //assign binary encoded codes to the states A through D parameter    A = 2'b00,    B = 2'b01,    C = 2'b10,    D = 2'b11; reg [1 : 0] current_state, next_state; //Section 1: Next state generator (NSG)...

  • Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset,...

    Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset, clk, TB, TA, output reg [1:0] LB, LA); reg [1:0] cstate, nstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; parameter grn = 2'b00; parameter ylw = 2'b01; parameter rd = 2'b10; // state register always @ (posedge clk, posedge reset) begin if (reset) cstate <= S0; else cstate <= nstate; end // next state logic...

  • 1. [20 Pts] You are given the data-path below. Note that there are three registers. Two of these have a load control input, while the other loads a new value on every clock cycle. There are two t...

    1. [20 Pts] You are given the data-path below. Note that there are three registers. Two of these have a load control input, while the other loads a new value on every clock cycle. There are two tri-state drivers that connect the outputs of registers A and Bto a common bus. Finally, there is an ALU that can perform two operations: .Pass Y add X and Y X is always the output of register C, while Y is the value...

  • Use Modelsim to debug and compile a while loop statement syntax: while (< expression >) <...

    Use Modelsim to debug and compile a while loop statement syntax: while (< expression >) < statement > module while_example (); reg [5:0] location; reg [7:0] data; always @ (data or location) begin location = 0;//If Data is 0, then location is 32 (invalid value) if (data == 0) begin location = 32; end else begin while (data [0] == 0) begin location = location + 1; data = data >> 1; end end $display ("DATA = %b LOCATION =...

  • Write a testbench for LFShift shift register example module 1f3r input clk, input reset, output a...

    Write a testbench for LFShift shift register example module 1f3r input clk, input reset, output a ); reg (5:0] shift; wire xor_sum; assign xor_sum = shift[1] ^ shift[4]; // feedback taps always @ (posedge clk) if (reset) shift <= 6'b111111; // initialize LFSR else shift <= { xor_sum, shift [5:1] }; // shift right assign a = shift[0]; // output of LFSR endmodule

  • Lab Description Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Af...

    Lab Description Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and use your ALU from Lab 3 to create an accumulator-based processor. This will act ike a simple processor; the ALU will execute si operations and each result will be stored in the register. In an accumulator, the value of the register will be updated with each operation; the register is used as an input to the...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT