Question

Write a testbench for LFShift shift register example

module 1f3r input clk, input reset, output a ); reg (5:0] shift; wire xor_sum; assign xor_sum = shift[1] ^ shift[4]; // feedback taps always @ (posedge clk) if (reset) shift <= 6'b111111; // initialize LFSR else shift <= { xor_sum, shift [5:1] }; // shift right assign a = shift[0]; // output of LFSR endmodule

Answer 1

A test bench is written in verilog code to provide set of inputs or stimuli to check the logic of the code and which can be run across different types of simulators.

module tb();

input clk;

forever //for producing clock of time period of 20 units

#10 clk = ~clk;

initilal

begin

reset = 1; shift[1] =1;

@(posedge clock);

#2;

reset = 0; shift[1] = 0;

@(posedge clk);

#2; //we can give any amount of delay after giving one stimulus

reset = 1;

@(posedge clock);

#2;

end

endmodule

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