Question

Please help to complete the code and write the testbench to design the following adder.

1.In this section, you add pipeline stage. 8 bits are used at every pipeline stage.Use the following template to complete your Verilog coding.
// Addition of two 16 bit, 2's complement nos., n1 and n2. 8 bits addition at a time. Result is 17 bits.
module adder_b (clk, n1, n2, sum) ;
input clk ;
input [15:0] n1 ;
input [15:0] n2 ;
output [16:0] sum ;
reg [16:0] sum ;
wire [8:0] sum_LSB ;
reg [8:0] sum_LSB_1 ;
reg [15:8] n1_reg1 ;
reg [15:8] n2_reg1 ;
wire [16:8] sum_MSB ;
wire [16:0] sum_next ;
assign sum_LSB = ____ ; // Add least 8 significant bits. sum_LSB [8] is the carry.
always @ (posedge clk) // Pipeline 1, clk (1), register LSB to continue addition of MSB.
begin
sum_LSB_1 <= _________; // Preserve LSB sum
n1_reg1 <= __________; // Preserve MSBs of n1
n2_reg1 <= __________;// Preserve MSBs of n2

end
// Extend sign & add msbs with carry.
assign sum_MSB = ____________________; // Add MSBs with carry.
assign sum_next = _____________________;
always @ (posedge clk) // Pipeline 2, clk (2), register result.
begin
sum <= ___________;
end
endmodule

Answer 1

// Addition of two 16 bit, 2's complement nos., n1 and n2. 8 bits addition at a time. Result is 17 bits.

module adder_b (clk, n1, n2, sum) ;

//input port declarations

input clk ;

input [15:0] n1 ;

input [15:0] n2 ;

//output port declarations

output [16:0] sum ;

reg [16:0] sum ;

//internal signal declarations  

wire [8:0] sum_LSB ;

reg [8:0] sum_LSB_1 ;

reg [15:8] n1_reg1 ;

reg [15:8] n2_reg1 ;

wire [16:8] sum_MSB ;

wire [16:0] sum_next ;

  

assign sum_LSB = n1[7:0] + n2[7:0] ; // Add least 8 significant bits. sum_LSB [8] is the carry.

always @ (posedge clk) // Pipeline 1, clk (1), register LSB to continue addition of MSB.

begin

sum_LSB_1 <= sum_LSB ; // Preserve LSB sum

n1_reg1 <= n1[15:8]; // Preserve MSBs of n1

n2_reg1 <= n2[15:8];// Preserve MSBs of n2

end

  

// Extend sign & add msbs with carry.

assign sum_MSB = n1_reg1 + n2_reg1 + sum_LSB_1[8] ; // Add MSBs with carry.

assign sum_next = {sum_MSB , sum_LSB_1[7:0]} ;

  

always @ (posedge clk) // Pipeline 2, clk (2), register result.

begin

sum <= sum_next;

end

endmodule

// verilog testbench code for given adder module

module test_adder;

//inputs

reg clk;

reg [15:0] n1;

reg [15:0] n2;

  

wire [16:0] sum;

  

//instantiate DUT

adder_b DUT (.clk(clk),.n1(n1),.n2(n2),.sum(sum));

  

  

//clock generation

initial begin

clk = 0;

forever #5 clk = ~clk;

end

  

//2's complement binary inputs

initial begin

$dumpfile ("");

$dumpvars;

n1 = 16'd11; n2 = 16'd13 ;#20;

n1 = 16'd01; n2 = 16'd67 ;#20;

n1 = 16'd9; n2 = 16'd56 ;#20;

n1 = 16'd53; n2 = 16'd56 ;#20;

n1 = 16'd67; n2 = 16'd43 ;#20;

n1 = 16'd87; n2 = 16'd13 ;#20;

$finish;

end

  

  

endmodule

  

  

  

// Simulation waveforms

From: Ons To: 120ns Get Signals Radix 100% X\ 100 20 60 80 40 cik 1010111 ni[15:0 nz[13:0 10Ai 1000011 110101 1001 101011 1101 1111000 1000011 1101 00100 1101110 000100 1101101 11000 1000001 sum[16:01 XxxXXX XxXxxx Note: To revert to EPWave opening in a new browser window, set that option on your user page