Please explain what he verilog code does: module lab7_2_3( input clk, input Enable, input Clear, input...
Please explain what he verilog code does:
module lab7_2_3(
input clk,
input Enable,
input Clear,
input Load,
output [3:0] Q,
reg [3:0] count,
wire cnt_done
);
assign cnt_done = ~| count;
assign Q = count;
always @(posedge clk)
if (Clear)
count <= 0;
else if (Enable)
if (Load | cnt_done)
count <= 4'b1010; // decimal 10
else
count <= count - 1;
Endmodule
Homework Answers
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Please explain what he verilog code does:
module lab7_2_3(
input clk,
input Enable,
input Clear,
input...
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR,...
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR, sel, Q); input CLK, PR, sel; output reg [2:0] Q; reg [2:0] y; assign Q = y; always @ (posedge PR, posedge CLK) begin if (PR== 1) then y <= 3'b111; else if (sel) begin y[2] <= y[1] ^ y[0]; y[1] <= y[2]; y[1]; end else y[2] <= y[2] ; y[1] <= y[1]; y[0]; y[O] <= y[0] <= end endmodule
3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left,...
3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q; input [7:0] Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<= Data_in; else case ( { Shift_left, Shift_right }) 2'600: if (Clk == 1) Q<=Q; 2'b01: if (Clk == 1) Q<= >> 1; 2'b10: if (Clk == 1) Q<=Q<< 1; default: Q<=Q; endcase endmodule a) What does reg (7:0] Q do? b)...
Write a testbench for LFShift shift register example module 1f3r input clk, input reset, output a...
Write a testbench for LFShift shift register
example
module 1f3r input clk, input reset, output a ); reg (5:0] shift; wire xor_sum; assign xor_sum = shift[1] ^ shift[4]; // feedback taps always @ (posedge clk) if (reset) shift <= 6'b111111; // initialize LFSR else shift <= { xor_sum, shift [5:1] }; // shift right assign a = shift[0]; // output of LFSR endmodule
Answer the question below for the following code, What does reg (7:0) do? What does always...
Answer the question below for the following code, What does reg (7:0) do? What does always @ (posedge Cik) do? C What causes 2"b01: if (Clk 1) Q<= >> 1 to execute? When it executes, what does it do module Shift_Register (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q, input (7:0) Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<Data_in; else case ( { Shift_left, Shift_right)) 2'600: if (Clk - 1)...
a Read the following codes in Verilog and the corresponding testbench file. Describe what the codes...
a Read the following codes in Verilog and the corresponding testbench file. Describe what the codes are doing by adding comments in the code. Then write down the simulation results of res1, res2, res3, and res4, respectively. Source code module vector_defn (num1, res1, res2, res3, res4); input [7:0] num1; output res1; output [3:0] res2; output [0:7] res3; output [15:0] res4; assign res1=num1[2]; assign res2=num1[7:4]; assign res3=num1; assign res4={2{num1}}; endmodule testbench: `timescale 1ns / 1ps module vector_defn_tb; reg [7:0] in1; wire...
Question 3: Realize the circuit below using Verilog. Include a signal “reset_n” for asynchronously clearing the...
Question 3: Realize the circuit below using Verilog. Include a signal “reset_n” for asynchronously clearing the flip-flop. What type of circuit is this? Complete the following Verilog code. Write a test bench to test it. clk sel module aff (clk, reset_n, sel, q); input clk ; // Declare the inputs and outputs of the module. input reset_n; input sel; output q; reg q; wire D; ; // model the combinational logic assign D= always @( begin if ( else end...
Write the verilog code that implements a negitive edge D-Flip Flop with asynchronous active low preset...
Write the verilog code that implements a negitive edge D-Flip Flop with asynchronous active low preset and clear I have : module dff( preset, clear, clk, D, Q) input preset; input clear; input clk; input D; output Q; reg Q; always @ (negedge clk or negedge preset or negedge clear); if (preset); Q = 0; else (clear == 0); Q = D; endmodule I honestly just want to know if i'm doing this right or not, if im not correct,...
Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset,...
Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset, clk, TB, TA, output reg [1:0] LB, LA); reg [1:0] cstate, nstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; parameter grn = 2'b00; parameter ylw = 2'b01; parameter rd = 2'b10; // state register always @ (posedge clk, posedge reset) begin if (reset) cstate <= S0; else cstate <= nstate; end // next state logic...
I need help writing a test bench for the following Verilog code module CU(IE, WE, WA,...
I need help writing a test bench for the following Verilog code module CU(IE, WE, WA, RAE, RAA, RBE, RBA, ALU, SH, OE, start, clk, reset, Ng5); //nG5 denotes (N>5); input start, clk, reset; output IE, WE, RAE, RBE, OE; output [1:0] WA, RAA, RBA, SH; output [2:0] ALU; input wire Ng5; reg [1:0] state; reg [1:0] nextstate; parameter S0 = 3'b000; parameter S1 = 3'b001;...
why its 4-to-1 mux behavioral? What does the logic circuit represented by the following Verilog module...
why its 4-to-1 mux behavioral?
What does the logic circuit represented by the following Verilog module do, and what Verilog description style does it use? // My Verilog module #1 module mymodl ( x, d, q) input[1:0] x;input[3:0] d;output q; reg q; wire [1:0] x; wire [3:0] d; always ( x or d) begin case ( x ) 1 : q=d[1]; 2 : g=d[2]; 3 q d[3]; endcase end endmodule
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR, sel, Q); input CLK, PR, sel; output reg [2:0] Q; reg [2:0] y; assign Q = y; always @ (posedge PR, posedge CLK) begin if (PR== 1) then y <= 3'b111; else if (sel) begin y[2] <= y[1] ^ y[0]; y[1] <= y[2]; y[1]; end else y[2] <= y[2] ; y[1] <= y[1]; y[0]; y[O] <= y[0] <= end endmodule
3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q; input [7:0] Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<= Data_in; else case ( { Shift_left, Shift_right }) 2'600: if (Clk == 1) Q<=Q; 2'b01: if (Clk == 1) Q<= >> 1; 2'b10: if (Clk == 1) Q<=Q<< 1; default: Q<=Q; endcase endmodule a) What does reg (7:0] Q do? b)...
Write a testbench for LFShift shift register
example
module 1f3r input clk, input reset, output a ); reg (5:0] shift; wire xor_sum; assign xor_sum = shift[1] ^ shift[4]; // feedback taps always @ (posedge clk) if (reset) shift <= 6'b111111; // initialize LFSR else shift <= { xor_sum, shift [5:1] }; // shift right assign a = shift[0]; // output of LFSR endmodule
Answer the question below for the following code, What does reg (7:0) do? What does always @ (posedge Cik) do? C What causes 2"b01: if (Clk 1) Q<= >> 1 to execute? When it executes, what does it do module Shift_Register (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q, input (7:0) Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<Data_in; else case ( { Shift_left, Shift_right)) 2'600: if (Clk - 1)...
Question 3: Realize the circuit below using Verilog. Include a signal “reset_n” for asynchronously clearing the flip-flop. What type of circuit is this? Complete the following Verilog code. Write a test bench to test it. clk sel module aff (clk, reset_n, sel, q); input clk ; // Declare the inputs and outputs of the module. input reset_n; input sel; output q; reg q; wire D; ; // model the combinational logic assign D= always @( begin if ( else end...
why its 4-to-1 mux behavioral?
What does the logic circuit represented by the following Verilog module do, and what Verilog description style does it use? // My Verilog module #1 module mymodl ( x, d, q) input[1:0] x;input[3:0] d;output q; reg q; wire [1:0] x; wire [3:0] d; always ( x or d) begin case ( x ) 1 : q=d[1]; 2 : g=d[2]; 3 q d[3]; endcase end endmodule
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