Question

1&2 and please I need quickly.

Q1 (35 pts): Design a combinational circuit that takes 8 bits of input and checks iif the inputs are symmetric or not and produces an output immediately. Example: 10011001 or 11000011 produce 1 and 11011010 or 11001100 produce 0.) (a) Write Verilog RTL for this circuit. (b) Same functionality but output appears next cycle. You can instantiate the design in part a. (c) Same functionality but output appeurs after two cycles. You can instantiate the design in part a. (d) Implement the functionality in part a by instantiating AND2, OR2, XOR2, NOT gates. 02 (30 pts): I want to implement a circuit that counts the number of posedges of the clock signal. Also, when I press the stop button, the circuit stops counting until I release the button. (a) Complete the code below. Do not modify the existing lines. Don't worry about the counter wrapping around. Just fill in the always blocks. module posEdgeCounter (clk, stop, ent); input clk; input stop; output reg (2:0) ont; reg (2:0) entNext; always e (posedge alk) begin end always e(*) begin end endmodule (b) Draw the bubble diagram of the code, (c) What is the maximum value of out can get?

Answer 1

// vexilog code to detect Symmetric or not Il solution for (a) Module Solution a input (1:01 ini, Output out Il four 2 input Xor gates wie bo = int [1] ^ in con; wire by = int [6] ^ itu; wire ba - int (5) ^ in1 (11; wire bg - in lui^ int(3]: Il four inverters wire 6.no = ~bai wire b_1 = ~by wire bana = rubai wire bang = ~63; Il Three 2 input and gates wire ando = 6.no & bals wire and _1 = 6.18 6.13) assign out and and 1 end module Il Solution for (6) Module Solution- input (1:0) in Output reg Out wire a-out; ll using Solutionia) Solution_a u-solutional ini lini ), .out (Q-out) ) always @ (Posedge clk) out E a out: end Module input clk;

Il solution for (1) Module Solution input ck, input (7:0] ini, output reg out wiXC Q_out; reg delay_flop; ll using Solution (a) Solution a u-Solution al ing Cina ), outla-out) ); always @ Po {out, delay_flop 3 €{delay_flop, g-out'}; endmodule [ Solution module for Id solution de input (1:0] ina, output out XOY 1.9. (bo, in C+1, inalol) xor ug (bi, in1 (61 , in 1(11); YOY U-9. (62, ina(5] in1(23) XOV U-9, 162, inacul, in 113]); not uino (b.no, bo); not u-inu, (6.0, bili not ucinu (6.1₂, b.); not u inv3 (6.03,63); and u.gu (and-o, 6.no, 6-ni); and u-gg (and-1, 6-₂, 6-13); and U-96 (out, and o, and 1); end module