![Verilog Assignment l. (a) Use Modelsim to debug and compile a while loop statement syntax while expression statement module while example reg [5:0] location reg [7:0] data. always (data or location) begin. location If Data is 0, then location is 32 (invalid value) if (data 0) begin location. 32 end else begin while (data [0] 0) begin location. location 1. data data 1 end end. display (DATA 8b LOCATION d, data, location) end initial begin #1 data. 8 b11 #1 data. 8 b100 #1 data. 8 b1000 1 data. J: 8 b1000 0000 #1 data. 8 bo #1 finish; end endmodule (b) After running and simulating this code, printout the results. Provide explanation in a short paragraph (few lines) what this while example did (in the code), based on your output.](http://img.homeworklib.com/questions/93023c20-bc0f-11ec-8650-e16e803e34b9.png?x-oss-process=image/resize,w_560)
Homework Answers
After runnig this code i got the following output:
Data=00000011 LOCATION= 0
Data=00000001 LOCATION= 2
Data=00000001 LOCATION= 3
Data=00000001 LOCATION= 7
Data=00000000 LOCATION=32
so lets start with the first if condition, if data is 0 then location 32,as we can see the 5th data value is 0 location is 32.
coming to else part, while loop works as follows:
data[0] means first element of the data if it is 0 the increment location by 1 and perform binary right shift adding 0 to msb of the data say 00000011 >> 1 will give 00000001, this while continues till data[0] is 0.
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