Question

Each FF has an asynchronous active-low clear signal. The asynchronous active-low clear signal clears the FF and uses this signal to set the initial output of the FF to zero. (Active-low clear: clear when clear signal is low (0)).

Implement negative edge-triggered T FF using Verilog code. At this time,

The interface is as follows.

Module t_ff (input t, input clk, input clearb, output q);

How the waveform of q changes when the value of input t changes sequentially to 0, 1

Try using testbench. At this time, the period of clk, that is, the clock, is 200 ps. timescale

`timescale set to 100ps / 1ps. Simulate using Modelsim and plot the output waveform

Please verify by using. Submit your Verilog code (t_ff.v) and output waveform.

(1) Verilog code (t_ff.v).

(2) Testbench code (t_ff_tb.v)

(3) Execute (1) in ModelSim to output the waveform

Answer 1

0 itrie utyu

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