Homework Answers
1) 8 bits because 256 registers 28
2) 8 bits.
3) 64 bits, because data is 64 bits.
4) 64 lines.
Add Answer to:
Suppose we have a Register File that contains 256 registers. Each register stores 64 bits of data. In the register file...
Objective: Creating a register file (memory) using Verilog. The register file is made up of four registers and each...
Objective: Creating a register file (memory) using Verilog. The register file is made up of four registers and each register holds one nibble (half a byte, i.e., four bits) 3. Create a D flip-flop AD flip-flop holds 1 bit of data, and it only changes its data when the clock changes. We want a positive edge triggered flip-flop. Design your Verilog D flip-flop, so we will create them now. Enter the 2 to 4 line decoder. We will need two...
« 3 » Design a system bus for parallel transferring data between 6 registers, each register can storage 4 bits as a wor...
« 3 » Design a system bus for parallel transferring data between 6 registers, each register can storage 4 bits as a word A) Use MUX method in your design B) Use Tri-State method in your design
« 3 » Design a system bus for parallel transferring data between 6 registers, each register can storage 4 bits as a word A) Use MUX method in your design B) Use Tri-State method in your design
Question 1 Figure 1 shows a datapath for R-type instructions which consits of a register file...
Question 1 Figure 1 shows a datapath for R-type instructions which consits of a register file and an arithmetic logic unit (ALU). These instructions are also known as aritmetic-logical- instructions since they perform aritmetic or logical operations. The register file contains all the registers and provides two read ports and one write port. The register file always provides the contents of the registers corresponding to the read register inputs on the outputs, while the writes must be explicitly controlled with...
EEL4768C Lab Assignment 6 (40 points) Due 7/24/2018, 11:59 pm on Canvas Register file is an...
EEL4768C Lab Assignment 6 (40 points) Due 7/24/2018, 11:59 pm on Canvas Register file is an important state element of the MIPS processor. Consider the register file shown below. The register file can read and write the data into the registers. The register file has two read ports (A1, A2) and one write port (A3). The width of Al, A2 and A3 is 5 bits. Writing data into the register is synchronized with the clock signal. WE is the write...
1) We would like to design a bus system for 32 registers of 16 bits each....
1) We would like to design a bus system for 32 registers of 16 bits each. How many multiplexers are needed for the design? Select one: 5 16 1 4 32 2) The basic computer can be interrupted while another interrupt is being serviced. Select one: True False 3) If the Opcode bits of an instruction is 111, then the basic computer instruction type is either memory-reference or input-output. Select one: True False 4) The content of AC in the...
In this question, you are asked to construct a register file with one input port and...
In this question, you are asked to construct a register file with one input port and two output ports. The register file contains two registers and each register stores a 2-bit data. You are allowed to use D flip-flops, 2-to-1 1-bit MUXs, and 1-to-2 decoders with enable only. Draw a circuit diagram for the register file. Please label your diagram clearly (especially the signals on the MUXs and decoders).
Question 5 2 pts Following diagram illustrates the process of writing a register. Suppose all 5 b...
Question 5 2 pts Following diagram illustrates the process of writing a register. Suppose all 5 bits for "Register number" are high voltage and all 32 bits for "Register data" are low voltage. And we assume high voltage means 1 and low voltage means 0. Write 0 Register 0 n-to-2n. decoder Register number Register 1 Register n-2 Register n-1 Register data Question:s .When we apply high voltage to "Write" signal, which register(s) have their C input to be at high...
Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of...
Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of cache, and a block size of 16 bytes. For each configuration below, determine the memory address format, indicating the number of bits needed for each appropriate field (i.e. tag, block, set, offset). Show any relevant calculations. Direct cache mapping and memory is byte-addressable a) Direct cache mapping and memory is word-addressable with a word size of 16 bits b) c) 2-way set associative cache...
Suppose we have a hypothetical processor, of which each register has only five bits. r0 =...
Suppose we have a hypothetical processor, of which each register has only five bits. r0 = 0b11101 and r1 = 0b10110. What are the N,Z,C, and V flags of the following instructions? Assume initially N = 0, Z = 0, C = 1, V = 0, and these instructions are executed independently (1) ADDS r3, r0, r1 (2) SUBS r3, r0, r1 (3) EOR r3, r0, r1 (4) ANDS r3, r1, r1, LSL #3
Exercise 1 (9 pts) We have seen that ARM has 16*32 bits registers (plus floating point...
Exercise 1 (9 pts) We have seen that ARM has 16*32 bits registers (plus floating point registers) There is also a status register: CPSR. It contains, among other things, the following important status bits N Negative, set when the result of an arithmetic operation is negative (according to the two's complement encoding of the natural numbers . Z- Zero, set when the result of an operation is zero . C Carry, set when an operation results in a carry bit...
Objective: Creating a register file (memory) using Verilog. The register file is made up of four registers and each register holds one nibble (half a byte, i.e., four bits) 3. Create a D flip-flop AD flip-flop holds 1 bit of data, and it only changes its data when the clock changes. We want a positive edge triggered flip-flop. Design your Verilog D flip-flop, so we will create them now. Enter the 2 to 4 line decoder. We will need two...
« 3 » Design a system bus for parallel transferring data between 6 registers, each register can storage 4 bits as a word A) Use MUX method in your design B) Use Tri-State method in your design
« 3 » Design a system bus for parallel transferring data between 6 registers, each register can storage 4 bits as a word A) Use MUX method in your design B) Use Tri-State method in your design
Question 1 Figure 1 shows a datapath for R-type instructions which consits of a register file and an arithmetic logic unit (ALU). These instructions are also known as aritmetic-logical- instructions since they perform aritmetic or logical operations. The register file contains all the registers and provides two read ports and one write port. The register file always provides the contents of the registers corresponding to the read register inputs on the outputs, while the writes must be explicitly controlled with...
EEL4768C Lab Assignment 6 (40 points) Due 7/24/2018, 11:59 pm on Canvas Register file is an important state element of the MIPS processor. Consider the register file shown below. The register file can read and write the data into the registers. The register file has two read ports (A1, A2) and one write port (A3). The width of Al, A2 and A3 is 5 bits. Writing data into the register is synchronized with the clock signal. WE is the write...
Question 5 2 pts Following diagram illustrates the process of writing a register. Suppose all 5 bits for "Register number" are high voltage and all 32 bits for "Register data" are low voltage. And we assume high voltage means 1 and low voltage means 0. Write 0 Register 0 n-to-2n. decoder Register number Register 1 Register n-2 Register n-1 Register data Question:s .When we apply high voltage to "Write" signal, which register(s) have their C input to be at high...
Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of cache, and a block size of 16 bytes. For each configuration below, determine the memory address format, indicating the number of bits needed for each appropriate field (i.e. tag, block, set, offset). Show any relevant calculations. Direct cache mapping and memory is byte-addressable a) Direct cache mapping and memory is word-addressable with a word size of 16 bits b) c) 2-way set associative cache...
Exercise 1 (9 pts) We have seen that ARM has 16*32 bits registers (plus floating point registers) There is also a status register: CPSR. It contains, among other things, the following important status bits N Negative, set when the result of an arithmetic operation is negative (according to the two's complement encoding of the natural numbers . Z- Zero, set when the result of an operation is zero . C Carry, set when an operation results in a carry bit...
Most questions answered within 3 hours.
-
Assume one of your finals has 50 questions on it, and
lucky for you, it's all...
asked 34 minutes ago -
Rice Products in Bangladesh
Business behavior is derived in large part from the basic cultural
environment...
asked 1 hour ago -
The following base sequence is found for a mRNA fragment from
wild-type E. coli: 5'- UAUCAGUAGAUAAUGUAACC-3'...
asked 2 hours ago -
For this exercise, round all regression parameters to three
decimal places.
One of the two tables...
asked 2 hours ago -
What is the 5% level of significance for mean = 3.60, standard
deviation = 0.94, and...
asked 2 hours ago -
Prior to beginning work on this discussion, please read the
article by Hayley Peterson, 15 Companies...
asked 3 hours ago -
Which pair of aqueous solutions, when mixed, will form a
precipitate?
A) NaNO3 and AgC2H3O2
B)...
asked 3 hours ago -
1-Write an algorithm to get two numbers from the user (as
inputs) and calculate the sum...
asked 6 hours ago -
Define white-collar crime. What is the difference between
offender and offense-based definitions of white-collar crime? What...
asked 7 hours ago -
Consider a reaction which is 1st order with respect to A and 1st
order with respect...
asked 7 hours ago -
c++
The length of the hypotenuse of a right-angled triangle is the
square root of the...
asked 7 hours ago -
When a metal rod is heated, not only its resistance but also its
length and cross‐sectional...
asked 7 hours ago