Question

Verilog! NOT VHDL Please

(4 pts) Write a behavioral Verilog module to implement a counter that counts in the following sequence: 000, 010, 100, 110, 001, 011, 101, 111, (repeat) 000, etc. Use a ROM and D flip-flops. Create a test bench for your counter design and run functional simulation in ModelSim.

Answer 1

module counter (clock, reset, Q);

input clock, reset;

output [2:0] Q;

reg [2:0] ROM [7:0];

reg [2:0] address;

initial begin

ROM[3'b000] = 000;
ROM[3'b001] = 010;
ROM[3'b010] = 100;
ROM[3'b011] = 110;
ROM[3'b100] = 001;
ROM[3'b101] = 011;
ROM[3'b110] = 101;
ROM[3'b111] = 111;

end

always @ (posedge clock or reset)

begin

   if (reset)

       address <= 3'b000;
   else

       address <= address + 1'b1;
  
end

assign Q = ROM[address];

endmodule

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