Question

verilog code needed for the counter using the JK flip flop

Successfully completing a System Verilog +80Pts. Implementation showing the full sequence of ABC readouts Pre-Laboratory Exercise: You are to design a counter that will count through a sequence either forward or reverse. You will have two control inputs: Direction, and Reset'. Sequence #2: 000 100 110 111 101001 → 011 010 → 000... {Gray code} When Direction=0 follow the order listed above. When Direction = 1, reverse the direction of the count. When Reset=1 the counter should count normally. When Reset' the counter should be forced to the 000 state. Please consider using the asynchronous CLEAR function of the flip-flops for this task. You should design the counter two times, once using 74LS73 JK flip-flops and once using 74LS74 D flip-flops. Determine which design will be less complex to implement.

please include the testbench, thanks!

Answer 1

Design of counter of the given sequence * It has direction input (band * ff Direction). O then count sequence is gray code 000 91007110 1111101+001-2014 010 Repeat → It Direction ) input = 1 then Counter Sequences 000 4100 410-11-1014-001 010 Repeat * Siale diagram - considered initial State as "600" > States are assigned with plipflop output Q2 Q1 20 Initial state after Reset Dao lozi D-0 100 D-0 0-1 DRO DEL D= O 10 0 D-1 * Excitation table of Ik flip flop a at JK oo ox OLX Il XO

State Transition table Neutstalls J-k flipflopinpeche equipment + + Фt T2 и Tikip to oo 1х ох ох о то ох 1 6x о то - от present states Input Ф, , , p (0) o oo o (0 осо т (2) орто (5) оо | (ю сто о (6) ото (6) рі, (а) от 1 са) Тоо а) teo 1 (10) Соус () ( о т (1) {to о - - ox xxx o o11 o оо оо! ox x x po ту x ох . x оор. 001 11 т x xь ту хо хо хо Ty x x т (1) =) (51) . о 1,2 ООт 1 x qх тоо от 1 0x ox ox 1x г 12 : tro (, a ) + га (2,4 10, 1, 12, 13, 1415) 21 = Zra (+ d ( 1-25,6 1 - 2 (1,2,31) - 74 (+ 1 12 14 15) В4 = 2 ( 1 12 + b (o 1, 2, 344,6,1) 10 = L = 1 +7 (2 61 0,1,415) = arr(4,5) 24 (5,1,11 12 13) * D en Stales, are Coulos output 2016

K-map Simplification for gik flipflop inputs loop ProLUB 32 = 9tão o + ał go do J2 = a [ po @)) K2 = O POD +1 900 k2= a (ao 6 ) J= Q2 (2.60) + 02 (490) Kl = 02 (Q.) + 02 ( 1) flooo ono da K) x 1 x x JO - Q2Q10 + TERIO Ko = 0.00 + azalo ko - Q1 (Q0D)) T0 = Q1 (42 )

// verilog code for COUNTER using j-k flipfops

module counter(D,clk,Reset,count);

//input port declaartions

input D,clk,Reset ;

//output port declarations

output [2:0] count ;

  

//internal signal declarations for flipflop inputs

reg [2:0] J,K;

//internal signal declarations for flipflop outputs

reg [2:0] Q,Q_bar;

  

//logic for flipflop input expressions

assign J[2] = ((~Q[1]) & (~(Q[0] ^ D)));

assign K[2] = ((~Q[1]) & (Q[0] ^ D));

assign J[1] = ((Q[2] & (~(Q[0] ^ D))) | ((~Q[2]) & (Q[0] ^ D))) ;

assign K[1] = (((~Q[2]) & (~(Q[0] ^ D))) | (Q[2] & (Q[0] ^ D))) ;

assign J[0] = (Q[1] & (~(Q[2] ^ D)));

assign K[0] = (Q[1] & (Q[2] ^ D));

  

  

//INSTANTIATION of JK flipflops

JK_FF U0 (.J(J[2]),.K(K[2]),.clk(clk),.Reset(Reset),.Q(Q[2]),.Q_bar(Q_bar[2]));

JK_FF U1 (.J(J[1]),.K(K[1]),.clk(clk),.Reset(Reset),.Q(Q[1]),.Q_bar(Q_bar[1]));

JK_FF U2 (.J(J[0]),.K(K[0]),.clk(clk),.Reset(Reset),.Q(Q[0]),.Q_bar(Q_bar[0]));

//combo logic for counter output

assign count = Q;

  

endmodule

//verilog code for J-K flipflop

module JK_FF (J,K,clk,Reset,Q,Q_bar);

  

input J,K,clk,Reset;

output Q,Q_bar;

  

reg temp;

  

always @(posedge clk)

begin

if (Reset==1'b0)

begin

temp <= 1'b0;

end

else begin

case({J,K})

2'b00: temp <= temp;

2'b01: temp <= 1'b0;

2'b10: temp <= 1'b1;

2'b11: temp <= (~temp);

endcase

end

end

  

assign Q = temp ;

assign Q_bar = ~(Q);

  

endmodule

// verilog testbench code for counter

module test_counter ;

  

//inputs

reg D,clock,Reset ;

//outputs

wire [2:0] count;

  

//instantiate counter DUT

counter DUT (D,clock,Reset,count);

  

  

//clock input genartion

initial

begin

clock = 1'b0 ;

forever #5 clock = ~clock ;

end

  

  

initial

begin

$dumpfile("file.vcd");

$dumpvars;

Reset = 1'b0 ;

D=1'b1;#10;

Reset = 1'b1;

D=1'b0;

#80 ;

D= 1'b1;

#70;

D=1'b0;

$finish;

end

endmodule