Question

Using verilog code, write the testbench and design for a D- Flip Flop (latch)

Answer 1

Here I'm writing the d flip flop Test Bench along with the d flip flop code.For the test bench simulation we need to write the normal code of the asked flip flop.

If you have any doubts please comment below.

// D flip flop code;

module dff(clk,in,y);
input clk,in;
output y;
reg y;
always@(posedge clk)
begin
y=in ;
end
endmodule

//Test Bench for d flip flop;

module TB_dff( ); //In testbench we don't mention the net list;
reg clk,d;
wire out;
initial
begin
clk=0;
d=0;
#100000 $finish;
end
end
always #100 clk = ~ clk ;
always #330 d = ~ d ;
dff anyname(out, d, clk ) ; //Instantiation of the D flip flop;
endmodule