Question

Draw the gate level circuit schematic of a D flip-flop and a T flip-flop based on the cross-coupled NAND latch. Briefly discuss the timing behavior of a D flip-flop, a T flip-flop and a latch. (a) (8 Marks) circuit has three inputs, S, C and C2. S is the control input. When S-O, the circuit behaves like a D flip-flop, and when S-1, the circuit behaves like a T flip-flop. The input characteristics of the circuit are tabulated in Table 3 b) A Table 3: Input characteristics of the circuit Circuit Input D/T flip-flop Input Not used 0 C2 0 Not used i Tabulate the characteristic tables of both the D flip-flop and the T flip- flop. (ii) Draw the state diagram of the circuit. iii) Tabulate the excitation table of the circuit. (14 Marks) Briefly discuss the differences between a flip-flop and a latch in terms of their power dissipation. (c)

Answer 1

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