Question

a) Draw an SR-latch using only NAND gates. Label each input and output, and label all wires with a name if the wire does not connect to any input or output

b) Describe the behavior of the latch when S and R are both 0. What is the output of each gate?

c) Assuming that the latch starts with S = R = 0, write down the sequence of what happens when R = 1. Discuss changes at each point in the latch (for everything labeled in part a). The changes should be listed in order of time, and should continue until the latch state is stable (i.e., none of the labeled values will ever change, assuming that the values on S and R never change).

d) Repeat Part c, but assuming the latch start with S = R = 0, and write down the sequence of what happens when S = 1.

e) Will there be anything that changes (in terms of design, behavior, or timing) if this latch is in a master/slave flip-flop instead of a NOR gate based SR-latch? Why or why not?

Answer 1

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