Question

10.5 This refers to the S' input for the NAND version, i.e., you don't have to include an inverter for S. 10.8 Start with Q = 0, Q = 1. Hint: be sure to remember what you observed in the previous problem!

Answer 1

Answer, Glittle Given that. would your expect propagation set input to a output to be delay faster form in a Set - reset latch built from a pair of NAND gates ? gates or one built from a pair of Nor Explain =) NAND offers less delay as compared where (belay = {(9b+8) to Nor bg= logical Effort h = Electrical Effort = parasitic Delay to Delay unt which Constant is techealg, al g= n+2 2 for a trpent NAND 8= 2nto) for an input Wor hat for (NAND ON NOR). h=2 for (NAND and NOR) a

De lor NAND 1 x 1+2 here g=n+2 Considering n=2; t(gh+P) =) 1 (2+2 x 1+2) De log NAND = 4(7 +1+2) here gant 2 54(+3) T EH itlu+6) 2 n=2 lucht p=2 T Derry Wand = lot omne 2 Delos wor = t (ght P) substitute v hip values =) & (2nti h+P) n=2, h=1, p=2 -) + (212) + 1 x 1+2) =) + (8 +1 +2] = £ { // +6] -) + Honda 1rY Delay NoR =) 11t I 3 u =) Hence, NAND offers Les De

{ with out delay] (with dolay]