Question

Name: (4) (10 pts) Design a Moore FSM that has one input A and one output Y, and the output Y should be 1 if A has been 101 during the most recent three consecutive clock cycles or A has been 1 during the two most recent consecutive clock cycles. You only need to write down your state transition diagram. (5) (6 pts) Consider the following sequential circuit. Each two-input OR gate has a propagation delay of 130ps and a contamination delay of 40ps. The inverter has a propagation delay of 80ps and a contamination delay of 20ps. Each two-input AND gate has a propagation delay of 110ps and a contamination delay of 30ps. Each D flip-flop has a setup time of 80ps, a hold time of 30ps, a clock-to-Q propagation delay tpog of 50ps, and a clock- to-Q contamination delay tecq of 40ps. Note that 1ps-10-12 second. If there is no clock skew, what is the maximum operating frequency of the circuit? How much clock skew can the circuit tolerate before it might experience a hold time violation?

Answer 1

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