Question

1.

a) Complete the waveform templates for the Master –Slave D-flip-flop below with given D, CLK, CLEAR, and PRESET signals. Neglect the propagation delays.

b) Does it have positive or negative edge triggering with respect to CLK?

c) Are the asynchronous PRESET and CLEAR active-high or active-low?

PRESET CLEAR U1 QM bar U4 T6 U2 TG 01 I02 1 102 TG TG CLK CLK barD CLK CLK bar CLEAR PRESE QM_bar

2. Enabling of data load in the D-flip-flop was implemented with a 2-to-1 multiplexer as show below. The D-flip-flop has the positive edge triggering and the active-low asynchronous clear.

a) Is the Enable input active-high or active-low?

b) Obtain the flip—flop characteristic equation: express the next state Q* in terms of D, E, and Q.

c) Complete the waveform template, neglect the propagation delays.

3)

For the synchronous finite state machine below

a) Identify the type of output Z (Mealy, Moore).
b) Obtain the state diagram: show states, transitions between states with X= 0 and 1, and output Z. c) Estimate the maximum clock frequency for the reliable operation when the setup and hold times are met and the system follows the state diagram transitions. Assume the setup time of 70 ns, the hold time of +10 ns, the D to Q propagation delay of 55 ns, the XOR delay of 25 ns.
d) Complete the waveform template, neglect the propagation delays.

4)

In the finite state machine below the D-flip-flop outputs serve as output of the system.
a) Obtain the state diagram. Upon initialization the flip-flops were cleared
b) Estimate the maximum clock frequency for the reliable operation. Assume the setup time of 50 ns, the hold time of -10 ns, the D to Q propagation delay of 55 ns, the AND2 gate delay of 25 ns, the NAND2 delay of 20 ns.
c) Complete the waveform template, asynchronous clear is active-high, neglect the propagation delays.

Answer 1