Question

3. Answer the following questions about a data flip-flop (D-Flip Flop): a) (4 ps) Write the VHDL required to define a rising-edge triggered (RET) D-Flip Flop with additional clock enable (CEN) and reset inputs. Your reset may be synchronous or asynchronous. Assume any input, output, or signal variables that you require have already been declared in VHDL (you do not have to write the declarations for these) b) [I pal ls your reset syachronous or asynchronous for the D-Flip Flop you defined in part a? Briefly explain your answer c) [2 pts] Complete the next four clock cycles of "Q" in the timing diagram for the D-Flip Flop you defined in part a: CLK 05 CEN RESET 0ns 100 ns 200 ns 300 ns 400n

Answer 1

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