Question

Make a RAM with the help of Flip flop using behavioral modeling on Verilog.

The code should be simple as I am a beginner. Also, I need an urgent answer is required.

Answer 1

The behavioral modeling can be done with 2 ways:-

1> Synchronous clear:- Output will reset at triggered edge(can be positive edge or negative edge).

2> Asynchronous clear:- Clear signal is independent of clock.

Here,To make the RAM, I have used D flip fop with Synchronous clear in which output will reset at positive edge of clock.

Code

module dff_behavioral(d,clk,clear,q,qbar); 
input d, clk, clear; 
output reg q, qbar; 
always@(posedge clk) 
begin
if(clear== 1)
q <= 0;
qbar <= 1;
else 
q <= d; 
qbar = !d; 
end 
endmodule

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