Question

5. Write the Verilog code using the behavioral algorithmic approach based on a simple loop. 6. Write the testbench code to test the design in (5).

Answer 1

Priority Encoder(8:3)

Verilog design :

module priority_enco(
input en,
input [3:0]in,
output reg v,
output reg [1:0]out );

    integer i;
    
    always@(*) begin
       if(!en) begin
            out = 2'b00;
            v =1'b0;  
       end
       else
       begin :block1
           for (i=3; i>=0; i= i-1) begin
                //Priority Logic. each Time It will check Whether the MSB bit is active, If so it will break //the loop. Otherwise It will decrement and continue the same
                if (in[i]==1'b1) begin
                case (i)
                     3: begin out = 2'b11; v= 1'b1; end
                     2: begin out = 2'b10; v= 1'b1; end
                     1: begin out = 2'b01; v= 1'b1; end
                     0: begin out = 2'b00; v= 1'b1; end
                    default :begin out = 2'bxx; v= 1'bx; end
                endcase
                
                disable block1;
                //Disable statement is synthesizible
                
                end  
           end
          
       end
    end

endmodule

Test bench :

module tb_prior_enco ;
    
    reg en;
    reg  [2:0]in;
    wire [1:0] out;
    wire v;
    
    priority_enco  PRIOR_ENC (.en(en),.in(in),.out(out),.v(v));
    
    initial begin
        en =0;
        in =0;
        repeat(19)
        random_generation(in,en);
        #65 $finish;
    end
    
    
    task random_generation;

//Generating random values
    output [3:0]in_t;
    output en_t;
    begin
        #4;
        in_t = $random % 4;
        en_t =$random;
    end
    endtask
    
    task display;
    input en_t;
    input [3:0]in_t;
    input [1:0]out_t;
    input v_t;
    
        $display("time =%0t \t INPUT VALUES \t en =%b in =%b \t OUTPUT VALUES out =%b v =%b",$time,en_t,in_t,out_t,v_t);
    
    endtask
    
    always@(out)
       display(en,in,out,v);
    
endmodule