Question

Can someone help me design a gate level circuit and model using HDL? It needs to convert 3-bit gray code to a binary number representation 2) adds the gray code input to its binary representation3) includes a flag(output)to determine when an overflow occurs.

For example 111 in gray code is 5 in base 10, the binary representation for 5 is 101, the sum is 1100, an overflow has occurred and the overflow bit is set to 1.

You will show as timing diagram outputs,1)the inputs, 2) the converted binary representation, 3) the resulting sum, and 4) the overflow flag.

Answer 1

Structure: (Using XOR Gate)

Truth table:

G1	G2	G3	B1	B2	B3
0	0	0	0	0	0
1	0	0	0	0	1
1	1	0	0	1	0
0	1	0	0	1	1
0	1	1	1	0	0
1	1	1	1	0	1
1	0	1	1	1	0
0	0	1	1	1	1

VHDL Code:

library ieee;

entity G2B is

port(

gray:in bit_vector(2 downto 0);

bin:out bit_vector(2 downto 0)

);

end G2B;

architecture dataflow of G2B is

begin

bin(2)<=gray(2);

bin(1)<=gray(2) xor gray(1);

bin(0)<=gray(3) xor gray(2) xor gray(1) xor gray(0);

end dataflow;

Timing Diagram: