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Write a VERILOG simulation code for a 3 to 8 decoder and a simulation code for a 4 to 16 decoder using two 3 to 8 decoders.

The code used for 3 to 8 decoder:

22 module Dec3to8 ( 23 input [2:0 A input E output [7:0] D 24 25 26 27 E &A[2]& 28 assign D[0] A[1 A[0] E &A[2] &A[1] assign

Code used for 4 to 16 decoder:

xDec3to8.v Schematic (2) Schematic (3) Project Summary Schematic Dec4to16.v X X X E:/EEE3342X/Lab_5/Test 1/Test 1.srcs/source

Need help with simulation code.

22 module Dec3to8 ( 23 input [2:0 A input E output [7:0] D 24 25 26 27 E &A[2]& 28 assign D[0] A[1 A[0] E &A[2] &A[1] assign D[1] & A[0] 29 E & A[2] & A[1] & A[0]; 30 assign D[2] assign D[3 E & A[2] & A[1] & A[0]; 31 & A[1 ~A[0] E & A[2]& A[1] & A[0] E & A[2] 32 assign D[4] 33 assign D[5] assign D[6] assign D[7] = E & A[2] 34 A[1 A[01 & A[1 A[0] E &A[2] 35 endmodule 36 37
xDec3to8.v Schematic (2) Schematic (3) Project Summary Schematic Dec4to16.v X X X E:/EEE3342X/Lab_5/Test 1/Test 1.srcs/sources_1/new/Dec4to16.v 13 // /Dependencies: 14 15 //Revision: 16 //Revision 0.01 - File Created 17 //Additional Comments: 18 // 19 20 21 22 23 module Dec4tol6 ( input [3:0 A output [15:0] D 24 25 26 Dec3t08 decl ( .A (A[2:01, .E (A[3]), .D(D [15:8])); Dec3t08 dec2(.A (A[2:01), .E(~A [3]), .D(D[7:0])) 27 28 29 endmodule 30
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Answer #1

//Testbench

`timescale 1ns/1ps

module Dec4to16_tb();

   reg [3:0] A;
   wire [15:0] D;

   Dec4to16 dec1(.A(A), .D(D));
  
   initial
   begin
   A <= 4'b0000;
   #5;
   A <= 4'b0001;
   #5;
   A <= 4'b0010;
   #5;
   A <= 4'b0011;
   #5;
   A <= 4'b0100;
   #5;
   A <= 4'b0101;
   #5;
   A <= 4'b0110;
   #5;
   A <= 4'b0111;
   #5;
   A <= 4'b1000;
   #5;
   A <= 4'b1001;
   #5;
   A <= 4'b1010;
   #5;
   A <= 4'b1011;
   #5;
   A <= 4'b1100;
   #5;
   A <= 4'b1101;
   #5;
   A <= 4'b1110;
   #5;
   A <= 4'b1111;
   #5;
   end

endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Simulation

M ModelSim INTEL FPGA STARIER EDITION 10.5b File Edit View Compile Simulate Add Wave Tools Lavout Bookmarks Window Help 3 E.

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