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Write Verilog modules: a 3x8 decoder and a 8x1 multiplexor. The multiplexor “includes” the decoder module...

Write Verilog modules: a 3x8 decoder and a 8x1 multiplexor. The multiplexor “includes” the decoder module as part of it. Use arrays as much as possible.

EXAMPLE:

module DecoderMod(s, o); // module definition
   input s;
   output [0:1] o;

   not(o[0], s);
   assign o[1] = s;
endmodule

module MuxMod(s, d, o);
   input s;
   input [0:1] d;
   output o;

   wire [0:1] s_decoded, and_out;

   DecoderMod my_decoder(s, s_decoded); // create instance

   and(and_out[0], d[0], s_decoded[0]);
   and(and_out[1], d[1], s_decoded[1]);
   or(o, and_out[0], and_out[1]);
endmodule
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Answer #1 
module Multiplexer_1(I0,I1,I2,I3,I4,I5,I6,I7,s3,s2,s1,y,en)
input I0,I1,I2,I3,s2,s1,en;
output y;
assign y=((~s3)&(~s2)&(~s1)&en&I0)| ((~s3)&(~s2)&(s1)&en&I1)|((~s3)&s2&(~s1)&en&I2)|((~s3)&(s2)&(s1)&en&I3)|((s3)&(~s2)&(~s1)&en&I4)|((s3)&(~s2)&(s1)&en&I5)|((s3)&(s2)&(~s1)&en&I6)|((s3)&(s2)&(s1)&en&I7);
end module
Multiplexer_1 Decoder(
.I0(I0),
.I1(I1),
.I2(I2),
.I3(I3),
.I4(I4),
.I5(I5),
.I6(I6),
.I7(I7)
);
        input a,b,c;
        output d0,d1,d2,d3,d4,d5,d6,d7;
        assign   I0=(~a&~b&~c),
                         I1=(~a&~b&c),
                         I2=(~a&b&~c),
                         I3=(~a&b&c),
                         I4=(a&~b&~c),
                         I5=(a&~b&c),
                         I6=(a&b&~c),
                         I7=(a&b&c);
end
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