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program an 8-to-1 multiplexor using verilog

output of time table from 1 - 2047

For example output should look like....

--------- [Start of table] ---------------------------- [End of table] ----------

Time 0 00000000 ססס ססס .1 1ססססססס ס1סססססס ססס .2 11סססססס ססס .3 4. 000 00000100 101ססססס ססס .5 110ססססס ססס .6 7. 000 009 9 1998. 111 1999. 111 2000. 111 2001. 2003. 111 2005. 111 2006. 111 2007. 111 2008 111 2009. 111 2010. 111 2011, 111 2012.

Here is example of 4x1 Multiplexor ... Just need code for 8x1 Multiplexor

module DecoderMod(s, o);
input [1:0] s;
output [0:3] o;
wire [1:0] inv_s;

not(inv_s[1], s[1]);
not(inv_s[0], s[0]);
and(o[0], inv_s[1], inv_s[0]);
and(o[1], inv_s[1], s[0]);
and(o[2], s[1], inv_s[0]);
and(o[3], s[1], s[0]);
endmodule

module MuxMod(s, d, o);
input [1:0] s;
input [0:3] d;
output o;

wire [0:3] s_decoded, and_out;

DecoderMod my_decoder(s, s_decoded);

and(and_out[0], d[0], s_decoded[0]);
and(and_out[1], d[1], s_decoded[1]);
and(and_out[2], d[2], s_decoded[2]);
and(and_out[3], d[3], s_decoded[3]);

or(o, and_out[0], and_out[1], and_out[2], and_out[3]);
endmodule

module TestMod;
reg [1:0] s;
reg [0:3] d;
wire o;

MuxMod my_mux(s, d, o);

initial begin
$display("Time s. d... o");
$display("---- -- ---- -");
$monitor("%4d %b %b %b", $time, s, d, o);
end

always begin d[3] = 0; #1; d[3] = 1; #1; end
always begin d[2] = 0; #2; d[2] = 1; #2; end
always begin d[1] = 0; #4; d[1] = 1; #4; end
always begin d[0] = 0; #8; d[0] = 1; #8; end
always begin s[0] = 0; #16; s[0] = 1; #16; end
always begin s[1] = 0; #32; s[1] = 1; #32; end
initial #63 $finish; // terminates after 63 cycles
endmodule

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Homework Answers

Answer #1
  1. module mux8to1( Out,
  2. Sel,
  3. In1,
  4. In2,
  5. In3,
  6. In4,
  7. In5,
  8. In6,
  9. In7,
  10. In8
  11. );
  12. input [7:0] In1,
  13. In2,
  14. In3,
  15. In4,
  16. In5,
  17. In6,
  18. In7,
  19. In8; //The eight 8-bit input lines of the Mux
  20. input [2:0] Sel; //The three bit selection line
  21. output [7:0] Out; //The single 8-bit output line of the Mux
  22. reg [7:0] Out;
  23. //Check the state of the input lines
  24. always @ (In1 or In2 or In3 or In4 or In5 or In6 or In7 or In8 or Sel)
  25. begin
  26. case (Sel)
  27. 3'b000 : Out = In1;
  28. 3'b001 : Out = In2;
  29. 3'b010 : Out = In3;
  30. 3'b011 : Out = In4;
  31. 3'b100 : Out = In5;
  32. 3'b101 : Out = In6;
  33. 3'b110 : Out = In7;
  34. 3'b111 : Out = In8;
  35. default : Out = 8'bx;
  36. //If input is undefined then output is undefined
  37. endcase
  38. end
  39. endmodule
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