![Question 3 (3 marks) Identify at least 3 errors in the Verilog modules below. module simpleALU(mput [31:0) A, B, input [2:0) F, output reg [31:0) Y) endmodule module alu simpleTestbenchO; wire [10:0] inA, inB wire [2:0] sel; reg [31-0] outY simpleALU dut(sel, outY, inA, inB) initial (sel, inA, inB)-: #10 sei 3.6010; (inA, inB) - 16h0000 0000 0000 0000; #10 sel 3bl 10; finA, inB)- 16h0000 0000 FFFF_FFFF: endmodule](http://img.homeworklib.com/questions/b4490d30-c383-11ea-830c-65f4ae537118.png?x-oss-process=image/resize,w_560)
Homework Answers
1. dut i.e. simpleALU inputs A, B are 32 bit ports but mapped to inA, inB are 11 bit wire in test bench. Hence data gets truncated if we do such map.
2. dut is instantiated in test bench using positional mapping of ports but mapping is wrong. e.g. sel and outY getting mapped to inputs A,B
3. In testbench inA, inB , sel are declared as wire . It should be reg type . Else data can't be changed on them
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Question 3 (3 marks) Identify at least 3 errors in the Verilog modules below. module simpleALU(mput...
Question 3: Realize the circuit below using Verilog. Include a signal “reset_n” for asynchronously clearing the...
Question 3: Realize the circuit below using Verilog. Include a signal “reset_n” for asynchronously clearing the flip-flop. What type of circuit is this? Complete the following Verilog code. Write a test bench to test it. clk sel module aff (clk, reset_n, sel, q); input clk ; // Declare the inputs and outputs of the module. input reset_n; input sel; output q; reg q; wire D; ; // model the combinational logic assign D= always @( begin if ( else end...
7. Which of the following Verilog code segments will generate errors when compiled? A. module demo...
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Write Verilog modules: a 3x8 decoder and a 8x1 multiplexor. The multiplexor “includes” the decoder module...
Write Verilog modules: a 3x8 decoder and a 8x1 multiplexor. The multiplexor “includes” the decoder module as part of it. Use arrays as much as possible. EXAMPLE: module DecoderMod(s, o); // module definition input s; output [0:1] o; not(o[0], s); assign o[1] = s; endmodule module MuxMod(s, d, o); input s; input [0:1] d; output o; wire [0:1] s_decoded, and_out; DecoderMod my_decoder(s, s_decoded); // create instance and(and_out[0], d[0], s_decoded[0]); and(and_out[1], d[1], s_decoded[1]); or(o, and_out[0], and_out[1]); endmodule
why its 4-to-1 mux behavioral? What does the logic circuit represented by the following Verilog module...
why its 4-to-1 mux behavioral?
What does the logic circuit represented by the following Verilog module do, and what Verilog description style does it use? // My Verilog module #1 module mymodl ( x, d, q) input[1:0] x;input[3:0] d;output q; reg q; wire [1:0] x; wire [3:0] d; always ( x or d) begin case ( x ) 1 : q=d[1]; 2 : g=d[2]; 3 q d[3]; endcase end endmodule
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR,...
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR, sel, Q); input CLK, PR, sel; output reg [2:0] Q; reg [2:0] y; assign Q = y; always @ (posedge PR, posedge CLK) begin if (PR== 1) then y <= 3'b111; else if (sel) begin y[2] <= y[1] ^ y[0]; y[1] <= y[2]; y[1]; end else y[2] <= y[2] ; y[1] <= y[1]; y[0]; y[O] <= y[0] <= end endmodule
Please explain what he verilog code does: module lab7_2_3( input clk, input Enable, input Clear, input...
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Draw the circuit corresponding to the Verilog module below. (Do not attempt to simplify the circuit.)...
Draw the circuit corresponding to the Verilog module below. (Do not attempt to simplify the circuit.) module Circuit A (e, F, G, H); parameter n= 3; input [n-1:0] F, G; input e; output reg [n-1:0] H; integer k; always @ (e, F, G) begin for (k=0; k<n; k=k+1) H[k] = (e | F[k]) & G[k]; end endmodule
3. (10 Points) RTL Combinational Circuit Design a Draw the schematic for the Verilog code given...
3. (10 Points) RTL Combinational Circuit Design a Draw the schematic for the Verilog code given below: module abc (a, b, c, d, si, s0); input 31, 30; output a, b, c,d; not (51_, 51), (50_, 0); and (a, s1_, SO_); and (b, s1_, 0); and (c, sl, s0_); and (d, sl, s0); endmodule b. Draw the schematic for the Verilog code given below: module Always_Code input a, b, c, output reg F ); always @(a, b, c) begin F...
I need help writing a test bench for the following Verilog code module CU(IE, WE, WA,...
I need help writing a test bench for the following Verilog code module CU(IE, WE, WA, RAE, RAA, RBE, RBA, ALU, SH, OE, start, clk, reset, Ng5); //nG5 denotes (N>5); input start, clk, reset; output IE, WE, RAE, RBE, OE; output [1:0] WA, RAA, RBA, SH; output [2:0] ALU; input wire Ng5; reg [1:0] state; reg [1:0] nextstate; parameter S0 = 3'b000; parameter S1 = 3'b001;...
I need the following in verilog. Attached is also the test bench. CODE // Design a...
I need the following in verilog. Attached is also the test bench. CODE // Design a circuit that divides a 4-bit signed binary number (in) // by 3 to produce a 3-bit signed binary number (out). Note that // integer division rounds toward zero for both positive and negative // numbers (e.g., -5/3 is -1). module sdiv3(out, in); output [2:0] out; input [3:0] in; endmodule // sdiv3 TEST BENCH module test; // these are inputs to "circuit under test" reg...
Question 3: Realize the circuit below using Verilog. Include a signal “reset_n” for asynchronously clearing the flip-flop. What type of circuit is this? Complete the following Verilog code. Write a test bench to test it. clk sel module aff (clk, reset_n, sel, q); input clk ; // Declare the inputs and outputs of the module. input reset_n; input sel; output q; reg q; wire D; ; // model the combinational logic assign D= always @( begin if ( else end...
7. Which of the following Verilog code segments will generate errors when compiled? A. module demo output reg F, input a): ire b; reg c assign b-c; initial begin end endmodule module demo5 output reg F, input reg a); ire b reg c assign bC; initial begin end C. module demooutput reg F, input wire a ire b reg c assign b c; initial begin F c& b; end D. O both A) and C) E. O none will generate...
why its 4-to-1 mux behavioral?
What does the logic circuit represented by the following Verilog module do, and what Verilog description style does it use? // My Verilog module #1 module mymodl ( x, d, q) input[1:0] x;input[3:0] d;output q; reg q; wire [1:0] x; wire [3:0] d; always ( x or d) begin case ( x ) 1 : q=d[1]; 2 : g=d[2]; 3 q d[3]; endcase end endmodule
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR, sel, Q); input CLK, PR, sel; output reg [2:0] Q; reg [2:0] y; assign Q = y; always @ (posedge PR, posedge CLK) begin if (PR== 1) then y <= 3'b111; else if (sel) begin y[2] <= y[1] ^ y[0]; y[1] <= y[2]; y[1]; end else y[2] <= y[2] ; y[1] <= y[1]; y[0]; y[O] <= y[0] <= end endmodule
Draw the circuit corresponding to the Verilog module below. (Do not attempt to simplify the circuit.) module Circuit A (e, F, G, H); parameter n= 3; input [n-1:0] F, G; input e; output reg [n-1:0] H; integer k; always @ (e, F, G) begin for (k=0; k<n; k=k+1) H[k] = (e | F[k]) & G[k]; end endmodule
3. (10 Points) RTL Combinational Circuit Design a Draw the schematic for the Verilog code given below: module abc (a, b, c, d, si, s0); input 31, 30; output a, b, c,d; not (51_, 51), (50_, 0); and (a, s1_, SO_); and (b, s1_, 0); and (c, sl, s0_); and (d, sl, s0); endmodule b. Draw the schematic for the Verilog code given below: module Always_Code input a, b, c, output reg F ); always @(a, b, c) begin F...
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