Question

2. What is wrong with the following code (More than one error may exist in each seg module mux2_1 (10, 11, S, Y); input 10, 11, S; output Y; lalways @ (posedge s) begin if (S) Y=11; else Y=10; end endmodule module ESM (clk, a, outi, out2): input clk, a: output outi, outi: jalways @ (posedge clk) begin 1 if(state=0) begin if (a) state<=1; end 1 else begin if (-a) states : end end end Jalways @ (state) begin if (state=0) outl=1; else out2=1; end endmodule

Answer 1

2. What is wrong with the following code (More than one error may exist in each seg a) module mux2_1 (10, 11, S, Y); input 10, 11, S: output Y: lalways @ (posedge s) begin if (S) Y=11; else Y=10; end endmodule

2X1

The above code should be for the mux.

the below high lighted line is the wrong because mux is a combinational circuit and there is no rule that it should be triggered at the positive edge and there is no rule that it should work as a sequential circuit. It just requires high and low voltage. Therefore that always block is not at all necessary and only if statement is enough to execute the mux command.

!always @ (posedge s) begin is a wrong line remove that always block and execute.

In the above code mux is a combinational circuit and always block behaving for sequential circuit.

remove that block

module mux2_1 (I0,I1,s,y);

input i0,i1,s;

output y

if(s) y=i1;

else y=i0;

endmodule

b) module FSM(elk, a, outi, out2): input clk, a; output outi, outi; jalways @ (posedge clk) begin if(state==0) begin if (a) state<=1; end } else begin if (-a) state<=0; end end end jalways @ (state) begin outl=1; if (state==0) else out2=1; end endmodule

The above code is for the finite state machine.

if statement block doesnot contain being block and output should be out1,out2 and not identation for if statement needed.

original code should be like this

module FSM(clk,a,out1,out2);

input clk,a;

output out1,out2 ;

always @(posedge clk) begin

if(state ==0)

if(a) state<=1;

else

if(~a) state <=0;

end

always @(state)being

if(state==0) out1=1;

else out2=1;

end

endmodule