Question

17. The 74195 in Figure 17 is a synchronous load, 4-bit parallel-access shift register. For this exercise, the input data is loaded at the first active clock edge. (12 pts) 74195 DSTM2 SH/LD QB 13 QC QD DSTMI 10t CLK ㅡㅡㅡ CLR Figure 17 Use the circuit of Figure 17 to answer the following questions: a. Is this a ring counter or a Johnson counter? (2 pts) b. How many different states are available? (2 pts) Draw the timing diagram (four clock pulses) for the input as shown in the figure above. Use the space provided below. The timing diagram should include the clock and the valid outputs. (6 pts) (Hint: First, generate the truth table of clock pulse and the valid outputs c.

Answer 1

t data is loade at zevoth Pulse and jcte, shirtng hapPens at faling ed 2e at falling edge Sibol mean s 4i The date shed o Tc es us this table out Put S 3 K usn abore talle, lets draw the tdiagavn 6 data appears at the. output at this instant e 6 ち2 states pcatedONLY 4 distinct states

Please refer the datasheet. of the IC. type "74195 datasheet" in google and read the document for better understanding of the IC.

For drawing the above timing diagram, start at zeroth pulse and refer the table given above to determine the states of outputs at the falling edge of the clock. The IC is negative edge triggered and so the states change only at a falling edge of the clock.

Once the states change at the falling edge, they remain the same until next falling edge. The table provided above helps to find out how states will change at falling edge depending on J,K and Q0,Q1,Q2,Q3 values.

At any instant, J and K value equals value at Qc which is Q3 according to the datasheet. This is because J and K are connected to Qc

a)

for this 4 bit counter, there are only 4 distinct states and so it is a ring counter. If it was a johnson counter, we should have 8 states for 4 bit counter.

b)

It has 4 different states. For states, see the image attached.