Question

17. The 74195 in Figure 17 is a synchronous load, 4-bit parallel-access shift register. For this exercise, the input data is loaded at the first active clock edge. (12 pts) 74195 DSTM2 SH/LD 2 15 QC DSTMI 10 CLK CLR Figure 17 Use the circuit of Figure 17 to answer the following questions: a. Is this a ring counter or a Johnson counter? (2 pts) b. How many different states are available? (2 pts) Draw the timing diagram (four clock pulses) for the input as shown in the figure above. Use the space provided below. The timing diagram should include the clock and the valid outputs. (6 pts) (Hint: First, generate the truth table of clock pulse and the vali outputs) c. What is the duty cycle for each output line? (2 pts) d.

Answer 1

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