Question

Design a synchronous state machine which detects the serial bit sequence of 0 1 10 on the 1-bit input signal A (tested one bit at a time) and produces a "Moore-type positive-logic output of Y equal to 1 (and lasting just one clock period) only when that particular bit sequence is observed. At all other times, the output Y should be 0. The final 0 of the desired input sequence 0 110 can persist and become the first 0 of the next bit sequence, if A is stll 0 on the next tick of the clock. Note that the input signal A is asynchronous; that is, it can change .1 value at any time, independent of the clock (a) Provide an ASM chart of your design, including the state assignments/encodings (b) Implement your design in Verilog, using a synchronous, active high Clear capability to ensure that your machine can be started at a known, valid initial state. (c) Provide a Verilog test bench and simulation waveform out put to demonstrate the ability of your machine to correctly identify the input sequence, and to keep the output Y to 0 when an incorrect input sequence is provided.

Answer 1

(a)

The ASM chart

olo o/o 0 input/output rst Secondヽ 1/0 thndv ASM chart (state diagram)

(b)

//+++++++++++++Verilog code ++++++++++++++++//

`timescale 1ns / 1ps

module sequence_d(in,clk,rst,out
);
input clk,rst,in;
output reg out;
parameter reset=2'd0,first0=2'd1,second1=2'd2,third1=2'd3;
reg [1:0] p_state,n_state;

always @(posedge clk or posedge rst) begin
if(rst)
   p_state<=reset;
else
   p_state<=n_state;
end

always @(*) begin
case(p_state)
reset:begin
out=1'b0;
if(in)
   n_state=reset;
else
   n_state=first0;
end

first0:begin
out=1'b0;
if(in)
   n_state=second1;
else
   n_state=first0;
end

second1:begin
out=1'b0;
if(in)
   n_state=third1;
else
   n_state=first0;
end

third1:begin
if(in) begin
   n_state=reset;
   out=1'b0;
   end
else begin
   n_state=first0;
   out=1'b1;
   end
end

endcase
end

endmodule
//++++++++++++++END++++++++++++++++//

(c)

//+++++++++test bench+++++++++++++++//

`timescale 1ns / 1ps

module tb;

   // Inputs
   reg in;
   reg clk;
   reg rst;

   // Outputs
   wire out;

   // Instantiate the Unit Under Test (UUT)
   sequence_d uut (
       .in(in),
       .clk(clk),
       .rst(rst),
       .out(out)
   );

   initial begin
       // Initialize Inputs
       in = 0;clk = 0;rst = 1; #4
       in = 0;rst = 0; #4
       in = 0;rst = 0; #4
       in = 1;rst = 0; #4
       in = 1;rst = 0; #4
       in = 0;rst = 0; #40 $finish;
       end
always #1 clk=~clk;
  
endmodule

//++++++++++++++++++END+++++++++++++++++++//