Question

We want to design a circuit that takes as input a serial bit stream and outputs a 'l' whenever the sequence “111” occurs. Overlaps must also be considered. For instance, if... occurs, then the output should remain active for three consecutive clock cycles. 3.1) Draw the state diagram of the finite state machine. 3.2) Write the System Verilog model for the design.

Answer 1

3.1)

3.2) System Verilog code:-

module sequence_detector(in,clk,reset,y);
input in,clk,reset;
output y;
reg y;
reg [1:0] r,n;
parameter s0=2'b00,s1=2'b01,s2=2'b10;
always @(posedge clk or posedge reset)
if (reset)
r<= s0;

else
r<= n;
always @(r or in)
if (r ==s0 && in==0) n =s0;
else if (r ==s0 && in==1) n = s1;
else if (r ==s1 && in==0) n = s0;
else if (r ==s1 && in==1) n =s2;
else if (r ==s2 && in==0) n =s0;
else if (r ==s2 && in==1) n =s2;
always @(r or in)
if (r ==s2 && in==1) y=1;
else y=0;
endmodule

(Note: code is written in software , so it is errorfree).