Question

Using VHDL language, design, simulate and implement a “2-Digit up/down BCD seconds counter with reset button”circuit. The counter value must be automatically incremented/decremented twice every second (slow down the clock to 2 Hz). The up counting or down counting is determined by the status of a toggle switch on DE10-Lite board. If the toggle switch is set to logic 0 , the counter should count down and vice versa. In the up counting mode, if the counter reaches “59”, the counter should go to“00” for the next count. Similarly, in the down counting mode, when the counter reaches “00”, it should go back to “59” for the next count.

Answer 1

Answer :

Using VHDL language, design, simulate and implement a “2-Digit up/down BCD seconds counter with reset button”circuit. The counter value must be automatically incremented/decremented twice every second.

Design code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BCD_Counter is
port( Toggle: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
Output: out std_logic_vector(0 to 7));
end BCD_Counter;

architecture Behavioral of BCD_Counter is

signal temp_l: std_logic_vector(0 to 3);
signal temp_h: std_logic_vector(0 to 3);
begin process(Clock,Reset)
begin
if Reset='1' then
temp_l <= "0000";
temp_h <= "0000";
elsif(rising_edge(Clock)) then
if Toggle='0' then
if (temp_h="0000" and temp_l="0000") then
temp_h<= "0101";
temp_l<= "1001";
elsif temp_l="0000" then
temp_h <= temp_h - 1;
temp_l <= "1001";
else
temp_l <= temp_l - 1;
end if;
else
if (temp_h="0101" and temp_l="1001") then
temp_h<= "0000";
temp_l<= "0000";
elsif temp_l="1001" then
temp_h <= temp_h + 1;
temp_l <= "0000";
else
temp_l <= temp_l + 1;
end if;
end if;
end if;
end process;
Output <= temp_h & temp_l ;
end Behavioral;

Testbench:

library IEEE;
use IEEE.std_logic_1164.all;
entity tb_bcd_counters is
end tb_bcd_counters;
architecture Behavioral of tb_bcd_counters is
component BCD_Counter
Port ( Toggle: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
Output: out std_logic_vector(0 to 7));
end component;
signal Reset,Clock,Toggle: std_logic;
signal Output:std_logic_vector(0 to 7);
begin
dut: BCD_Counter port map (Toggle => Toggle, Clock => Clock, Reset=>Reset, Output => Output);
clock_process :process
begin
Clock <= '0';
wait for 0.25 * 1e9 ns;
Clock <= '1';
wait for 0.25 * 1e9 ns;
end process;
-- Stimulus process
stim_proc: process
begin   
-- hold reset state for 100 ns.
Reset <= '1';
wait for 2 * 1e9 ns;  
Reset <= '0';
wait for 2 * 1e9 ns;
Toggle <= '0';
wait for 50 * 1e9 ns;
Toggle <= '1';
wait;
end process;

end Behavioral;