Question

Q3: Using VHDL code, design a 4 bit BCD up counter using sequential statements (30 Marks) 0 012 03 C FF3 c( FFO

Answer 1

4bit counter

VHDL code

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity counter_4bit is

    port(

      clk : in STD_LOGIC;

      reset : in STD_LOGIC;

      dout : out STD_LOGIC_VECTOR(3 downto 0)

        );

end counter_4bit;

architecture counter_4bit_arc of counter_4bit is

begin

    counting : process (clk,reset) is

    variable m : std_logic_vector (3 downto 0) := "0000";

    begin

      if (reset='1') then

       m := "0000";

     elseif (rising_edge (clk)) then

       m := m + 1;

     end if;

     dout <= m;

end process counting;

end counter_4bit_arc;