Question

Module 72: Using this 4 Do bit up-counter, draw the Di diagram for a modulo counter which starts at 2 and counts up to 10, Load i.е., 2, 3, 4, 5, 6, 7, 8, 9, 10, 2, 3 0 D2 D3 Q2 Q3 Enable

Answer 1

Do 3 MoD-9 LOAD CIk Ena bie 3 -→ C3) う(S" O (6) ーーぅ(7)

Here I have assumed Q₀ to be the most significant bit(MSB) and Q₃ as the least significant bit.

Explanation:

A counter with a parallel load can be used to generate any desired count sequence. There is an additional COUNT control. The Count control is set to 1 to enable the count through the CLK input. Also we know that the Load control inhibits the count and that the clear operation is independent of other control inputs.
The AND gate detects the occurrence of state 1010. The counter is initially cleared to 2(i.e.preset to 0010), and then the Clear and Count inputs are set to 1, so the counter is active at all times.

As long as the output of the AND gate is 0, each positive‐edge clock increments the counter by 1. When the output reaches the count of 1010, both Q₀ and Q₂ become 1, making the output of the AND gate equal to 1.

Hence this condition will activate the Load input; therefore, on the next clock edge the register does not count, but is
loaded from its four inputs. Since inputs are connected to 0010 ,a reloading of the register occurs following the count of 0010.

Thus, the circuit goes through the count from 0010 through 1010 and back to 0010.

Number of states encountered are 9.Hence it is MOD-9 modulo counter.